Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Motorola MC5282EVB board. |
| 4 | * |
| 5 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
wdenk | 4e5ca3e | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 12 | #ifndef _CONFIG_M5282EVB_H |
| 13 | #define _CONFIG_M5282EVB_H |
| 14 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 15 | /* |
| 16 | * High Level Configuration Options |
| 17 | * (easy to change) |
| 18 | */ |
wdenk | 4e5ca3e | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 19 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 20 | #define CONFIG_SYS_UART_PORT (0) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 21 | |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 22 | #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 23 | |
| 24 | /* Configuration for environment |
| 25 | * Environment is embedded in u-boot in the second sector of the flash |
| 26 | */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 27 | |
angelo@sysam.it | 5296cb1 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 28 | #define LDS_BOARD_TEXT \ |
| 29 | . = DEFINED(env_offset) ? env_offset : .; \ |
Simon Glass | 0649cd0 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 30 | env/embedded.o(.text*); |
angelo@sysam.it | 5296cb1 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 31 | |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 32 | #ifdef CONFIG_MCFFEC |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 33 | # define CONFIG_SYS_DISCOVER_PHY |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 34 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
| 35 | # ifndef CONFIG_SYS_DISCOVER_PHY |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 36 | # define FECDUPLEX FULL |
| 37 | # define FECSPEED _100BASET |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 38 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 39 | #endif |
Jon Loeliger | 8353e13 | 2007-07-08 14:14:17 -0500 | [diff] [blame] | 40 | |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 41 | #ifdef CONFIG_MCFFEC |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 42 | # define CONFIG_IPADDR 192.162.1.2 |
| 43 | # define CONFIG_NETMASK 255.255.255.0 |
| 44 | # define CONFIG_SERVERIP 192.162.1.1 |
| 45 | # define CONFIG_GATEWAYIP 192.162.1.1 |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 46 | #endif /* CONFIG_MCFFEC */ |
| 47 | |
Mario Six | 5bc0543 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 48 | #define CONFIG_HOSTNAME "M5282EVB" |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 49 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 50 | "netdev=eth0\0" \ |
| 51 | "loadaddr=10000\0" \ |
| 52 | "u-boot=u-boot.bin\0" \ |
| 53 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 54 | "upd=run load; run prog\0" \ |
| 55 | "prog=prot off ffe00000 ffe3ffff;" \ |
| 56 | "era ffe00000 ffe3ffff;" \ |
| 57 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ |
| 58 | "save\0" \ |
| 59 | "" |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 60 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | #define CONFIG_SYS_CLK 64000000 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 62 | |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 63 | /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ |
| 64 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ |
| 66 | #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Low Level Configuration Settings |
| 70 | * (address mappings, register initial values, etc.) |
| 71 | * You should know what you are doing if you make changes here. |
| 72 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | #define CONFIG_SYS_MBAR 0x40000000 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 74 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 75 | /*----------------------------------------------------------------------- |
| 76 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 77 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 79 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 80 | |
| 81 | /*----------------------------------------------------------------------- |
| 82 | * Start addresses for the final memory configuration |
| 83 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 85 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 86 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 87 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 88 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 |
| 90 | #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 91 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 93 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 94 | /* |
| 95 | * For booting Linux, the board info and command line data |
| 96 | * have to be in the first 8 MB of memory, since this is |
| 97 | * the maximum mapped by the Linux kernel during initialization ?? |
| 98 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 100 | |
| 101 | /*----------------------------------------------------------------------- |
| 102 | * FLASH organization |
| 103 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 104 | #ifdef CONFIG_SYS_FLASH_CFI |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 105 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 107 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | # define CONFIG_SYS_FLASH_CHECKSUM |
| 109 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 110 | #endif |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 111 | |
| 112 | /*----------------------------------------------------------------------- |
| 113 | * Cache Configuration |
| 114 | */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 115 | |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 116 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 117 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 118 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 119 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 120 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) |
| 121 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ |
| 122 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 123 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 124 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ |
| 125 | CF_CACR_CEIB | CF_CACR_DBWE | \ |
| 126 | CF_CACR_EUSP) |
| 127 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 128 | /*----------------------------------------------------------------------- |
| 129 | * Memory bank definitions |
| 130 | */ |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 131 | #define CONFIG_SYS_CS0_BASE 0xFFE00000 |
| 132 | #define CONFIG_SYS_CS0_CTRL 0x00001980 |
| 133 | #define CONFIG_SYS_CS0_MASK 0x001F0001 |
| 134 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 135 | /*----------------------------------------------------------------------- |
| 136 | * Port configuration |
| 137 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ |
| 139 | #define CONFIG_SYS_PADDR 0x0000000 |
| 140 | #define CONFIG_SYS_PADAT 0x0000000 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 141 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ |
| 143 | #define CONFIG_SYS_PBDDR 0x0000000 |
| 144 | #define CONFIG_SYS_PBDAT 0x0000000 |
wdenk | 4e5ca3e | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 145 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ |
| 147 | #define CONFIG_SYS_PCDDR 0x0000000 |
| 148 | #define CONFIG_SYS_PCDAT 0x0000000 |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 149 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 150 | #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ |
| 151 | #define CONFIG_SYS_PCDDR 0x0000000 |
| 152 | #define CONFIG_SYS_PCDAT 0x0000000 |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 153 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_PEHLPAR 0xC0 |
| 155 | #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ |
| 156 | #define CONFIG_SYS_DDRUA 0x05 |
| 157 | #define CONFIG_SYS_PJPAR 0xFF |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 158 | |
| 159 | #endif /* _CONFIG_M5282EVB_H */ |