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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkbf9e3b32004-02-12 00:47:09 +00002/*
3 * Configuation settings for the Motorola MC5282EVB board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenkbf9e3b32004-02-12 00:47:09 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
wdenk4e5ca3e2003-12-08 01:34:36 +000012#ifndef _CONFIG_M5282EVB_H
13#define _CONFIG_M5282EVB_H
14
wdenkbf9e3b32004-02-12 00:47:09 +000015/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
wdenk4e5ca3e2003-12-08 01:34:36 +000019
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020020#define CONFIG_SYS_UART_PORT (0)
wdenkbf9e3b32004-02-12 00:47:09 +000021
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050022#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenkbf9e3b32004-02-12 00:47:09 +000023
24/* Configuration for environment
25 * Environment is embedded in u-boot in the second sector of the flash
26 */
wdenkbf9e3b32004-02-12 00:47:09 +000027
angelo@sysam.it5296cb12015-03-29 22:54:16 +020028#define LDS_BOARD_TEXT \
29 . = DEFINED(env_offset) ? env_offset : .; \
Simon Glass0649cd02017-08-03 12:21:49 -060030 env/embedded.o(.text*);
angelo@sysam.it5296cb12015-03-29 22:54:16 +020031
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050032#ifdef CONFIG_MCFFEC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033# define CONFIG_SYS_DISCOVER_PHY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
35# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050036# define FECDUPLEX FULL
37# define FECSPEED _100BASET
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050039#endif
Jon Loeliger8353e132007-07-08 14:14:17 -050040
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050041#ifdef CONFIG_MCFFEC
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050042# define CONFIG_IPADDR 192.162.1.2
43# define CONFIG_NETMASK 255.255.255.0
44# define CONFIG_SERVERIP 192.162.1.1
45# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050046#endif /* CONFIG_MCFFEC */
47
Mario Six5bc05432018-03-28 14:38:20 +020048#define CONFIG_HOSTNAME "M5282EVB"
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050049#define CONFIG_EXTRA_ENV_SETTINGS \
50 "netdev=eth0\0" \
51 "loadaddr=10000\0" \
52 "u-boot=u-boot.bin\0" \
53 "load=tftp ${loadaddr) ${u-boot}\0" \
54 "upd=run load; run prog\0" \
55 "prog=prot off ffe00000 ffe3ffff;" \
56 "era ffe00000 ffe3ffff;" \
57 "cp.b ${loadaddr} ffe00000 ${filesize};"\
58 "save\0" \
59 ""
wdenkbf9e3b32004-02-12 00:47:09 +000060
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_CLK 64000000
wdenkbf9e3b32004-02-12 00:47:09 +000062
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050063/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
66#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
wdenkbf9e3b32004-02-12 00:47:09 +000067
68/*
69 * Low Level Configuration Settings
70 * (address mappings, register initial values, etc.)
71 * You should know what you are doing if you make changes here.
72 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_MBAR 0x40000000
wdenkbf9e3b32004-02-12 00:47:09 +000074
wdenkbf9e3b32004-02-12 00:47:09 +000075/*-----------------------------------------------------------------------
76 * Definitions for initial stack pointer and data area (in DPRAM)
77 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +020079#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
wdenkbf9e3b32004-02-12 00:47:09 +000080
81/*-----------------------------------------------------------------------
82 * Start addresses for the final memory configuration
83 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkbf9e3b32004-02-12 00:47:09 +000085 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_SDRAM_BASE 0x00000000
87#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew012522f2008-10-21 10:03:07 +000088#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
90#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
wdenkbf9e3b32004-02-12 00:47:09 +000091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_MONITOR_LEN 0x20000
wdenkbf9e3b32004-02-12 00:47:09 +000093
wdenkbf9e3b32004-02-12 00:47:09 +000094/*
95 * For booting Linux, the board info and command line data
96 * have to be in the first 8 MB of memory, since this is
97 * the maximum mapped by the Linux kernel during initialization ??
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenkbf9e3b32004-02-12 00:47:09 +0000100
101/*-----------------------------------------------------------------------
102 * FLASH organization
103 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#ifdef CONFIG_SYS_FLASH_CFI
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108# define CONFIG_SYS_FLASH_CHECKSUM
109# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500110#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000111
112/*-----------------------------------------------------------------------
113 * Cache Configuration
114 */
wdenkbf9e3b32004-02-12 00:47:09 +0000115
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600116#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200117 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600118#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200119 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600120#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
121#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
122 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
123 CF_ACR_EN | CF_ACR_SM_ALL)
124#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
125 CF_CACR_CEIB | CF_CACR_DBWE | \
126 CF_CACR_EUSP)
127
wdenkbf9e3b32004-02-12 00:47:09 +0000128/*-----------------------------------------------------------------------
129 * Memory bank definitions
130 */
TsiChung Liew012522f2008-10-21 10:03:07 +0000131#define CONFIG_SYS_CS0_BASE 0xFFE00000
132#define CONFIG_SYS_CS0_CTRL 0x00001980
133#define CONFIG_SYS_CS0_MASK 0x001F0001
134
wdenkbf9e3b32004-02-12 00:47:09 +0000135/*-----------------------------------------------------------------------
136 * Port configuration
137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
139#define CONFIG_SYS_PADDR 0x0000000
140#define CONFIG_SYS_PADAT 0x0000000
wdenkbf9e3b32004-02-12 00:47:09 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
143#define CONFIG_SYS_PBDDR 0x0000000
144#define CONFIG_SYS_PBDAT 0x0000000
wdenk4e5ca3e2003-12-08 01:34:36 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
147#define CONFIG_SYS_PCDDR 0x0000000
148#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
151#define CONFIG_SYS_PCDDR 0x0000000
152#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_PEHLPAR 0xC0
155#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
156#define CONFIG_SYS_DDRUA 0x05
157#define CONFIG_SYS_PJPAR 0xFF
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500158
159#endif /* _CONFIG_M5282EVB_H */