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Michael Trimarchiaaf098c2008-11-28 13:20:46 +01001/*-
2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
Remy Böhmerc0d722f2008-12-13 22:51:58 +01003 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
Michael Trimarchiaaf098c2008-11-28 13:20:46 +01004 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef USB_EHCI_H
23#define USB_EHCI_H
24
Marek Vasutb9596552013-07-10 03:16:31 +020025#include <usb.h>
26
Remy Böhmerc0d722f2008-12-13 22:51:58 +010027#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
28#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
29#endif
30
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010031/*
32 * Register Space.
33 */
34struct ehci_hccr {
michaeldb632992008-12-10 17:55:19 +010035 uint32_t cr_capbase;
36#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
37#define HC_VERSION(p) (((p) >> 16) & 0xffff)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010038 uint32_t cr_hcsparams;
Remy Böhmerc0d722f2008-12-13 22:51:58 +010039#define HCS_PPC(p) ((p) & (1 << 4))
40#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
michael51ab1422008-12-11 13:43:55 +010041#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010042 uint32_t cr_hccparams;
43 uint8_t cr_hcsp_portrt[8];
Jason Kridner69716c12011-04-20 08:54:16 -050044} __attribute__ ((packed, aligned(4)));
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010045
46struct ehci_hcor {
47 uint32_t or_usbcmd;
michael51ab1422008-12-11 13:43:55 +010048#define CMD_PARK (1 << 11) /* enable "park" */
49#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
michael51ab1422008-12-11 13:43:55 +010050#define CMD_LRESET (1 << 7) /* partial reset */
Masahiro Yamadac02bf452014-11-05 23:11:10 +090051#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
52#define CMD_ASE (1 << 5) /* async schedule enable */
michael51ab1422008-12-11 13:43:55 +010053#define CMD_PSE (1 << 4) /* periodic schedule enable */
54#define CMD_RESET (1 << 1) /* reset HC not bus */
55#define CMD_RUN (1 << 0) /* start/stop HC */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010056 uint32_t or_usbsts;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020057#define STS_ASS (1 << 15)
Patrick Georgi8f62ca62013-03-06 14:08:31 +000058#define STS_PSS (1 << 14)
michael51ab1422008-12-11 13:43:55 +010059#define STS_HALT (1 << 12)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010060 uint32_t or_usbintr;
Damien Dusha29c6fbe2010-10-14 15:27:06 +020061#define INTR_UE (1 << 0) /* USB interrupt enable */
62#define INTR_UEE (1 << 1) /* USB error interrupt enable */
63#define INTR_PCE (1 << 2) /* Port change detect enable */
64#define INTR_SEE (1 << 4) /* system error enable */
65#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010066 uint32_t or_frindex;
67 uint32_t or_ctrldssegment;
68 uint32_t or_periodiclistbase;
69 uint32_t or_asynclistaddr;
Simon Glass9ab4ce22012-02-27 10:52:47 +000070 uint32_t _reserved_0_;
71 uint32_t or_burstsize;
72 uint32_t or_txfilltuning;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020073#define TXFIFO_THRESH_MASK (0x3f << 16)
Simon Glass9ab4ce22012-02-27 10:52:47 +000074#define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
75 uint32_t _reserved_1_[6];
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010076 uint32_t or_configflag;
michael51ab1422008-12-11 13:43:55 +010077#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
Remy Böhmerc0d722f2008-12-13 22:51:58 +010078 uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020079#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
80#define PORTSC_PSPD_FS 0x0
81#define PORTSC_PSPD_LS 0x1
82#define PORTSC_PSPD_HS 0x2
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010083 uint32_t or_systune;
Jason Kridner69716c12011-04-20 08:54:16 -050084} __attribute__ ((packed, aligned(4)));
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010085
michael51ab1422008-12-11 13:43:55 +010086#define USBMODE 0x68 /* USB Device mode */
87#define USBMODE_SDIS (1 << 3) /* Stream disable */
88#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
89#define USBMODE_CM_HC (3 << 0) /* host controller mode */
90#define USBMODE_CM_IDLE (0 << 0) /* idle state */
91
michaeldb632992008-12-10 17:55:19 +010092/* Interface descriptor */
93struct usb_linux_interface_descriptor {
94 unsigned char bLength;
95 unsigned char bDescriptorType;
96 unsigned char bInterfaceNumber;
97 unsigned char bAlternateSetting;
98 unsigned char bNumEndpoints;
99 unsigned char bInterfaceClass;
100 unsigned char bInterfaceSubClass;
101 unsigned char bInterfaceProtocol;
102 unsigned char iInterface;
103} __attribute__ ((packed));
104
105/* Configuration descriptor information.. */
106struct usb_linux_config_descriptor {
107 unsigned char bLength;
108 unsigned char bDescriptorType;
109 unsigned short wTotalLength;
110 unsigned char bNumInterfaces;
111 unsigned char bConfigurationValue;
112 unsigned char iConfiguration;
113 unsigned char bmAttributes;
114 unsigned char MaxPower;
115} __attribute__ ((packed));
116
117#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
michael51ab1422008-12-11 13:43:55 +0100118#define ehci_readl(x) (*((volatile u32 *)(x)))
119#define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b))
michaeldb632992008-12-10 17:55:19 +0100120#else
michael51ab1422008-12-11 13:43:55 +0100121#define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x))))
122#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \
123 cpu_to_le32(((volatile u32)b)))
michaeldb632992008-12-10 17:55:19 +0100124#endif
125
126#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
127#define hc32_to_cpu(x) be32_to_cpu((x))
128#define cpu_to_hc32(x) cpu_to_be32((x))
129#else
130#define hc32_to_cpu(x) le32_to_cpu((x))
131#define cpu_to_hc32(x) cpu_to_le32((x))
132#endif
133
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100134#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
135#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
136#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
137#define EHCI_PS_PO (1 << 13) /* RW port owner */
138#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
139#define EHCI_PS_LS (3 << 10) /* RO line status */
140#define EHCI_PS_PR (1 << 8) /* RW port reset */
141#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
142#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
143#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
144#define EHCI_PS_OCA (1 << 4) /* RO over current active */
145#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
146#define EHCI_PS_PE (1 << 2) /* RW port enable */
147#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
148#define EHCI_PS_CS (1 << 0) /* RO connect status */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100149#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
150
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100151#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100152
153/*
154 * Schedule Interface Space.
155 *
156 * IMPORTANT: Software must ensure that no interface data structure
157 * reachable by the EHCI host controller spans a 4K page boundary!
158 *
159 * Periodic transfers (i.e. isochronous and interrupt transfers) are
160 * not supported.
161 */
162
163/* Queue Element Transfer Descriptor (qTD). */
164struct qTD {
Wolfgang Denk3ed16072010-10-19 16:13:15 +0200165 /* this part defined by EHCI spec */
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200166 uint32_t qt_next; /* see EHCI 3.5.1 */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100167#define QT_NEXT_TERMINATE 1
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200168 uint32_t qt_altnext; /* see EHCI 3.5.2 */
169 uint32_t qt_token; /* see EHCI 3.5.3 */
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200170#define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
171#define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
172#define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
173#define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
174#define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
175#define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
176#define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
177#define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
178#define QT_TOKEN_PID_OUT 0x0
179#define QT_TOKEN_PID_IN 0x1
180#define QT_TOKEN_PID_SETUP 0x2
181#define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
182#define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
183#define QT_TOKEN_STATUS_ACTIVE 0x80
184#define QT_TOKEN_STATUS_HALTED 0x40
185#define QT_TOKEN_STATUS_DATBUFERR 0x20
186#define QT_TOKEN_STATUS_BABBLEDET 0x10
187#define QT_TOKEN_STATUS_XACTERR 0x08
188#define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
189#define QT_TOKEN_STATUS_SPLITXSTATE 0x02
190#define QT_TOKEN_STATUS_PERR 0x01
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200191#define QT_BUFFER_CNT 5
192 uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
193 uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
Wolfgang Denk3ed16072010-10-19 16:13:15 +0200194 /* pad struct for 32 byte alignment */
195 uint32_t unused[3];
Wolfgang Denk8b675fe2010-10-20 21:08:17 +0200196};
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100197
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200198#define EHCI_PAGE_SIZE 4096
199
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100200/* Queue Head (QH). */
201struct QH {
202 uint32_t qh_link;
203#define QH_LINK_TERMINATE 1
204#define QH_LINK_TYPE_ITD 0
205#define QH_LINK_TYPE_QH 2
206#define QH_LINK_TYPE_SITD 4
207#define QH_LINK_TYPE_FSTN 6
208 uint32_t qh_endpt1;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200209#define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
210#define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
211#define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
212#define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
213#define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
214#define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
215#define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
216#define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
217#define QH_ENDPT1_EPS_FS 0x0
218#define QH_ENDPT1_EPS_LS 0x1
219#define QH_ENDPT1_EPS_HS 0x2
220#define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
221#define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
222#define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100223 uint32_t qh_endpt2;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200224#define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
225#define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
226#define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
227#define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
228#define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100229 uint32_t qh_curtd;
230 struct qTD qh_overlay;
Stefan Roesedaa2daf2009-01-21 17:12:19 +0100231 /*
232 * Add dummy fill value to make the size of this struct
233 * aligned to 32 bytes
234 */
Patrick Georgi8f62ca62013-03-06 14:08:31 +0000235 union {
Vincent Palatin61755c72013-03-06 14:08:32 +0000236 uint32_t fill[4];
Patrick Georgi8f62ca62013-03-06 14:08:31 +0000237 void *buffer;
238 };
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100239};
240
Marek Vasutb9596552013-07-10 03:16:31 +0200241struct ehci_ctrl {
242 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
243 struct ehci_hcor *hcor;
244 int rootdev;
245 uint16_t portreset;
246 struct QH qh_list __aligned(USB_DMA_MINALIGN);
247 struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
248 uint32_t *periodic_list;
Hans de Goede36b73102014-09-20 16:51:25 +0200249 int periodic_schedules;
Marek Vasutb9596552013-07-10 03:16:31 +0200250 int ntds;
251};
252
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100253/* Low level init functions */
Troy Kisky127efc42013-10-10 15:27:57 -0700254int ehci_hcd_init(int index, enum usb_init_type init,
255 struct ehci_hccr **hccr, struct ehci_hcor **hcor);
Lucas Stach676ae062012-09-26 00:14:35 +0200256int ehci_hcd_stop(int index);
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100257
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100258#endif /* USB_EHCI_H */