blob: df59acae314bf553f54b7d7f06e6ddb0451e0d90 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk0ac6f8b2004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk0ac6f8b2004-07-09 23:27:13 +000025/*
26 * mpc8560ads board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000032 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000038#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050041#define CONFIG_CPM2 1 /* has CPM2 */
wdenk0ac6f8b2004-07-09 23:27:13 +000042#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
Kumar Galaf0600542008-06-11 00:44:10 -050043#define CONFIG_MPC8560 1
wdenk42d1f032003-10-15 23:53:47 +000044
wdenk0ac6f8b2004-07-09 23:27:13 +000045#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050046#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020047#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingccc091a2007-05-08 17:27:43 -050048#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000049#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060050#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Peter Tyser004eca02009-09-16 22:03:08 -050051#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk42d1f032003-10-15 23:53:47 +000052
wdenk0ac6f8b2004-07-09 23:27:13 +000053/*
54 * sysclk for MPC85xx
55 *
56 * Two valid values are:
57 * 33000000
58 * 66000000
59 *
60 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000061 * is likely the desired value here, so that is now the default.
62 * The board, however, can run at 66MHz. In any event, this value
63 * must match the settings of some switches. Details can be found
64 * in the README.mpc85xxads.
wdenk0ac6f8b2004-07-09 23:27:13 +000065 */
66
wdenk9aea9532004-08-01 23:02:45 +000067#ifndef CONFIG_SYS_CLK_FREQ
68#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000069#endif
70
wdenk9aea9532004-08-01 23:02:45 +000071
wdenk0ac6f8b2004-07-09 23:27:13 +000072/*
73 * These can be toggled for performance analysis, otherwise use default.
74 */
75#define CONFIG_L2_CACHE /* toggle L2 cache */
76#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk42d1f032003-10-15 23:53:47 +000079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
81#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000082
wdenk42d1f032003-10-15 23:53:47 +000083
84/*
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
87 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
90#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
91#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk42d1f032003-10-15 23:53:47 +000092
Jon Loeliger8b625112008-03-18 11:12:44 -050093/* DDR Setup */
94#define CONFIG_FSL_DDR1
95#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
96#define CONFIG_DDR_SPD
97#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000098
Jon Loeliger8b625112008-03-18 11:12:44 -050099#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
102#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000103
Jon Loeliger8b625112008-03-18 11:12:44 -0500104#define CONFIG_NUM_DDR_CONTROLLERS 1
105#define CONFIG_DIMM_SLOTS_PER_CTLR 1
106#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +0000107
Jon Loeliger8b625112008-03-18 11:12:44 -0500108/* I2C addresses of SPD EEPROMs */
109#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +0000110
Jon Loeliger8b625112008-03-18 11:12:44 -0500111/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
113#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
114#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
115#define CONFIG_SYS_DDR_TIMING_1 0x37344321
116#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
117#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
118#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
119#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000120
wdenk0ac6f8b2004-07-09 23:27:13 +0000121/*
122 * SDRAM on the Local Bus
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
125#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
128#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
131#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
132#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
133#undef CONFIG_SYS_FLASH_CHECKSUM
134#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
135#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
140#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000141#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000143#endif
144
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200145#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_CFI
147#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk0ac6f8b2004-07-09 23:27:13 +0000148
149#undef CONFIG_CLOCKS_IN_MHZ
wdenk42d1f032003-10-15 23:53:47 +0000150
wdenk42d1f032003-10-15 23:53:47 +0000151
wdenk0ac6f8b2004-07-09 23:27:13 +0000152/*
153 * Local Bus Definitions
154 */
155
156/*
157 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000159 *
160 * For BR2, need:
161 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
162 * port-size = 32-bits = BR2[19:20] = 11
163 * no parity checking = BR2[21:22] = 00
164 * SDRAM for MSEL = BR2[24:26] = 011
165 * Valid = BR[31] = 1
166 *
167 * 0 4 8 12 16 20 24 28
168 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
169 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000171 * FIXME: the top 17 bits of BR2.
172 */
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000175
176/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000178 *
179 * For OR2, need:
180 * 64MB mask for AM, OR2[0:7] = 1111 1100
181 * XAM, OR2[17:18] = 11
182 * 9 columns OR2[19-21] = 010
183 * 13 rows OR2[23-25] = 100
184 * EAD set for extra time OR[31] = 1
185 *
186 * 0 4 8 12 16 20 24 28
187 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
188 */
189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
193#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
194#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
195#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000196
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500197#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
198 | LSDMR_RFCR5 \
199 | LSDMR_PRETOACT3 \
200 | LSDMR_ACTTORW3 \
201 | LSDMR_BL8 \
202 | LSDMR_WRC2 \
203 | LSDMR_CL3 \
204 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000205 )
206
207/*
208 * SDRAM Controller configuration sequence.
209 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500210#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
211#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
212#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
213#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
214#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000215
wdenk42d1f032003-10-15 23:53:47 +0000216
wdenk9aea9532004-08-01 23:02:45 +0000217/*
218 * 32KB, 8-bit wide for ADS config reg
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_BR4_PRELIM 0xf8000801
221#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
222#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_INIT_RAM_LOCK 1
225#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
226#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
229#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
230#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
233#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000234
235/* Serial Port */
wdenk0ac6f8b2004-07-09 23:27:13 +0000236#define CONFIG_CONS_ON_SCC /* define if console on SCC */
237#undef CONFIG_CONS_NONE /* define if console on something else */
238#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
wdenk42d1f032003-10-15 23:53:47 +0000239
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200240#define CONFIG_BAUDRATE 115200
wdenk42d1f032003-10-15 23:53:47 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000243 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
244
245/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_HUSH_PARSER
247#ifdef CONFIG_SYS_HUSH_PARSER
248#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk42d1f032003-10-15 23:53:47 +0000249#endif
250
Matthew McClintock0e163872006-06-28 10:43:36 -0500251/* pass open firmware flat tree */
Kumar Gala5ce71582007-11-28 22:40:31 -0600252#define CONFIG_OF_LIBFDT 1
253#define CONFIG_OF_BOARD_SETUP 1
254#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_64BIT_VSPRINTF 1
257#define CONFIG_SYS_64BIT_STRTOUL 1
Jon Loeliger8b625112008-03-18 11:12:44 -0500258
Jon Loeliger20476722006-10-20 15:50:15 -0500259/*
260 * I2C
261 */
262#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
263#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk42d1f032003-10-15 23:53:47 +0000264#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
266#define CONFIG_SYS_I2C_SLAVE 0x7F
267#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
268#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk42d1f032003-10-15 23:53:47 +0000269
wdenk0ac6f8b2004-07-09 23:27:13 +0000270/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600271#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600272#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600273#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk42d1f032003-10-15 23:53:47 +0000275
wdenk0ac6f8b2004-07-09 23:27:13 +0000276/*
277 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300278 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000279 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600280#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600281#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600282#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600284#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600285#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
287#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000288
289#if defined(CONFIG_PCI)
290
wdenk42d1f032003-10-15 23:53:47 +0000291#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200292#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000293
294#undef CONFIG_EEPRO100
wdenk42d1f032003-10-15 23:53:47 +0000295#undef CONFIG_TULIP
wdenk0ac6f8b2004-07-09 23:27:13 +0000296
297#if !defined(CONFIG_PCI_PNP)
298 #define PCI_ENET0_IOADDR 0xe0000000
299 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200300 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000301#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000302
303#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000305
306#endif /* CONFIG_PCI */
307
308
Andy Flemingccc091a2007-05-08 17:27:43 -0500309#ifdef CONFIG_TSEC_ENET
wdenk0ac6f8b2004-07-09 23:27:13 +0000310
311#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200312#define CONFIG_NET_MULTI 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000313#endif
314
Andy Flemingccc091a2007-05-08 17:27:43 -0500315#ifndef CONFIG_MII
wdenk0ac6f8b2004-07-09 23:27:13 +0000316#define CONFIG_MII 1 /* MII PHY management */
Andy Flemingccc091a2007-05-08 17:27:43 -0500317#endif
Kim Phillips255a35772007-05-16 16:52:19 -0500318#define CONFIG_TSEC1 1
319#define CONFIG_TSEC1_NAME "TSEC0"
320#define CONFIG_TSEC2 1
321#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000322#define TSEC1_PHY_ADDR 0
323#define TSEC2_PHY_ADDR 1
324#define TSEC1_PHYIDX 0
325#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500326#define TSEC1_FLAGS TSEC_GIGABIT
327#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500328
329/* Options are: TSEC[0-1] */
330#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000331
Andy Flemingccc091a2007-05-08 17:27:43 -0500332#endif /* CONFIG_TSEC_ENET */
wdenk0ac6f8b2004-07-09 23:27:13 +0000333
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200334#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
Andy Flemingccc091a2007-05-08 17:27:43 -0500335
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200336#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk0ac6f8b2004-07-09 23:27:13 +0000337#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
338
339#if (CONFIG_ETHER_INDEX == 2)
wdenk42d1f032003-10-15 23:53:47 +0000340 /*
341 * - Rx-CLK is CLK13
342 * - Tx-CLK is CLK14
343 * - Select bus for bd/buffers
344 * - Full duplex
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
347 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
348 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
349 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk42d1f032003-10-15 23:53:47 +0000350 #define FETH2_RST 0x01
wdenk0ac6f8b2004-07-09 23:27:13 +0000351#elif (CONFIG_ETHER_INDEX == 3)
wdenk42d1f032003-10-15 23:53:47 +0000352 /* need more definitions here for FE3 */
353 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200354#endif /* CONFIG_ETHER_INDEX */
wdenk0ac6f8b2004-07-09 23:27:13 +0000355
Andy Flemingccc091a2007-05-08 17:27:43 -0500356#ifndef CONFIG_MII
357#define CONFIG_MII 1 /* MII PHY management */
358#endif
359
wdenk0ac6f8b2004-07-09 23:27:13 +0000360#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
361
wdenk42d1f032003-10-15 23:53:47 +0000362/*
363 * GPIO pins used for bit-banged MII communications
364 */
365#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200366#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
367 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
368#define MDC_DECLARE MDIO_DECLARE
369
wdenk42d1f032003-10-15 23:53:47 +0000370#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
371#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
372#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
373
374#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
375 else iop->pdat &= ~0x00400000
376
377#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
378 else iop->pdat &= ~0x00200000
379
380#define MIIDELAY udelay(1)
wdenk0ac6f8b2004-07-09 23:27:13 +0000381
wdenk42d1f032003-10-15 23:53:47 +0000382#endif
383
wdenk0ac6f8b2004-07-09 23:27:13 +0000384
385/*
386 * Environment
387 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200389 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200391 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
392 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000393#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200395 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200397 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000398#endif
399
wdenk0ac6f8b2004-07-09 23:27:13 +0000400#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000402
Jon Loeliger2835e512007-06-13 13:22:08 -0500403/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500404 * BOOTP options
405 */
406#define CONFIG_BOOTP_BOOTFILESIZE
407#define CONFIG_BOOTP_BOOTPATH
408#define CONFIG_BOOTP_GATEWAY
409#define CONFIG_BOOTP_HOSTNAME
410
411
412/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500413 * Command line configuration.
414 */
415#include <config_cmd_default.h>
416
417#define CONFIG_CMD_PING
418#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600419#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500420#define CONFIG_CMD_IRQ
421#define CONFIG_CMD_SETEXPR
Jon Loeliger2835e512007-06-13 13:22:08 -0500422
423#if defined(CONFIG_PCI)
424 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000425#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000426
Jon Loeliger2835e512007-06-13 13:22:08 -0500427#if defined(CONFIG_ETHER_ON_FCC)
428 #define CONFIG_CMD_MII
429#endif
430
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500432 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500433 #undef CONFIG_CMD_LOADS
434#endif
435
wdenk42d1f032003-10-15 23:53:47 +0000436
wdenk0ac6f8b2004-07-09 23:27:13 +0000437#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000438
439/*
440 * Miscellaneous configurable options
441 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kumar Gala22abb2d2007-11-29 10:34:28 -0600443#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
445#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk0ac6f8b2004-07-09 23:27:13 +0000446
Jon Loeliger2835e512007-06-13 13:22:08 -0500447#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000449#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000451#endif
452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
454#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
455#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
456#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk42d1f032003-10-15 23:53:47 +0000457
458/*
459 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500460 * have to be in the first 16 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000461 * the maximum mapped by the Linux kernel during initialization.
462 */
Kumar Gala89188a62009-07-15 08:54:50 -0500463#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
wdenk42d1f032003-10-15 23:53:47 +0000464
wdenk42d1f032003-10-15 23:53:47 +0000465/*
466 * Internal Definitions
467 *
468 * Boot Flags
469 */
470#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenk0ac6f8b2004-07-09 23:27:13 +0000471#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenk42d1f032003-10-15 23:53:47 +0000472
Jon Loeliger2835e512007-06-13 13:22:08 -0500473#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000474#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
475#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
476#endif
477
wdenk9aea9532004-08-01 23:02:45 +0000478
479/*
480 * Environment Configuration
481 */
482
wdenk0ac6f8b2004-07-09 23:27:13 +0000483/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000484#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500485#define CONFIG_HAS_ETH0
wdenk0ac6f8b2004-07-09 23:27:13 +0000486#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000487#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000488#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000489#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000490#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Kumar Gala5ce71582007-11-28 22:40:31 -0600491#define CONFIG_HAS_ETH3
492#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
wdenk42d1f032003-10-15 23:53:47 +0000493#endif
494
wdenk0ac6f8b2004-07-09 23:27:13 +0000495#define CONFIG_IPADDR 192.168.1.253
496
497#define CONFIG_HOSTNAME unknown
498#define CONFIG_ROOTPATH /nfsroot
499#define CONFIG_BOOTFILE your.uImage
500
501#define CONFIG_SERVERIP 192.168.1.1
502#define CONFIG_GATEWAYIP 192.168.1.1
503#define CONFIG_NETMASK 255.255.255.0
504
505#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
506
wdenk9aea9532004-08-01 23:02:45 +0000507#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
wdenk0ac6f8b2004-07-09 23:27:13 +0000508#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
509
510#define CONFIG_BAUDRATE 115200
511
wdenk9aea9532004-08-01 23:02:45 +0000512#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming6b44a442008-07-14 20:04:40 -0500513 "netdev=eth0\0" \
514 "consoledev=ttyCPM\0" \
515 "ramdiskaddr=1000000\0" \
516 "ramdiskfile=your.ramdisk.u-boot\0" \
517 "fdtaddr=400000\0" \
518 "fdtfile=mpc8560ads.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000519
wdenk9aea9532004-08-01 23:02:45 +0000520#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500521 "setenv bootargs root=/dev/nfs rw " \
522 "nfsroot=$serverip:$rootpath " \
523 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
524 "console=$consoledev,$baudrate $othbootargs;" \
525 "tftp $loadaddr $bootfile;" \
526 "tftp $fdtaddr $fdtfile;" \
527 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000528
529#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500530 "setenv bootargs root=/dev/ram rw " \
531 "console=$consoledev,$baudrate $othbootargs;" \
532 "tftp $ramdiskaddr $ramdiskfile;" \
533 "tftp $loadaddr $bootfile;" \
534 "tftp $fdtaddr $fdtfile;" \
535 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000536
537#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000538
539#endif /* __CONFIG_H */