blob: 70dd47ecb56b0886fd03b385fa9ff437fa54de13 [file] [log] [blame]
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +09001/*
2 * Configuation settings for the Renesas Solutions AP-325RXA board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __AP325RXA_H
27#define __AP325RXA_H
28
29#undef DEBUG
30#define CONFIG_SH 1
31#define CONFIG_SH4 1
32#define CONFIG_CPU_SH7723 1
33#define CONFIG_AP325RXA 1
34
35#define CONFIG_CMD_LOADB
36#define CONFIG_CMD_LOADS
37#define CONFIG_CMD_FLASH
38#define CONFIG_CMD_MEMORY
39#define CONFIG_CMD_NET
40#define CONFIG_CMD_PING
41#define CONFIG_CMD_NFS
42#define CONFIG_CMD_SDRAM
Mike Frysingerbdab39d2009-01-28 19:08:14 -050043#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090044#define CONFIG_CMD_IDE
45#define CONFIG_CMD_EXT2
46#define CONFIG_DOS_PARTITION
47
48#define CONFIG_BAUDRATE 38400
49#define CONFIG_BOOTDELAY 3
50#define CONFIG_BOOTARGS "console=ttySC2,38400"
51
52#define CONFIG_VERSION_VARIABLE
53#undef CONFIG_SHOW_BOOT_PROGRESS
54
55/* SMC9118 */
Ben Warren736fead2009-07-20 22:01:11 -070056#define CONFIG_NET_MULTI
57#define CONFIG_SMC911X 1
58#define CONFIG_SMC911X_32_BIT 1
59#define CONFIG_SMC911X_BASE 0xB6080000
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090060
61/* MEMORY */
62#define AP325RXA_SDRAM_BASE (0x88000000)
63#define AP325RXA_FLASH_BASE_1 (0xA0000000)
64#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
65
66/* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_LONGHELP
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090068/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_PROMPT "=> "
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090070/* Buffer size for input from the Console */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_CBSIZE 256
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090072/* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090074/* max args accepted for monitor commands */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_MAXARGS 16
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090076/* Buffer size for Boot Arguments passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_BARGSIZE 512
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090078/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090080
81/* SCIF */
82#define CONFIG_SCIF_CONSOLE 1
83#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
84#define CONFIG_CONS_SCIF5 1
85
86/* Suppress display of console information at boot */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#undef CONFIG_SYS_CONSOLE_INFO_QUIET
88#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
89#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
92#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090093
94/* Enable alternate, more extensive, memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#undef CONFIG_SYS_ALT_MEMTEST
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090096/* Scratch address used by the alternate memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#undef CONFIG_SYS_MEMTEST_SCRATCH
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090098
99/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900103/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900105/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900107
108/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900110/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900112/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900114/* size in bytes reserved for initial data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_GBL_DATA_SIZE (256)
116#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900117
118/* FLASH */
119#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_CFI
121#undef CONFIG_SYS_FLASH_QUIET_TEST
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900122/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_FLASH_EMPTY_INFO
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900124/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900126/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900128
129/*
130 * IDE support
131 */
132#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_PIO_MODE 1
134#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
135#define CONFIG_SYS_IDE_MAXDEVICE 1
136#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
137#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
138#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
139#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
140#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900141
142/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_MAX_FLASH_BANKS 1
144#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900145
146/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900148/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900150/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900152/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900154
155/*
156 * Use hardware flash sectors protection instead
157 * of U-Boot software protection
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#undef CONFIG_SYS_FLASH_PROTECTION
160#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900161
162/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200163#define CONFIG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900164#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200165#define CONFIG_ENV_SECT_SIZE (128 * 1024)
166#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
168/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
169#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200170#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900171
172/* Board Clock */
173#define CONFIG_SYS_CLK_FREQ 33333333
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +0200174#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Jean-Christophe PLAGNIOL-VILLARD8dd29c82009-06-04 12:06:47 +0200175#define CONFIG_SYS_HZ 1000
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900176
177#endif /* __AP325RXA_H */