blob: 473e364796f378ffe0a933cb7de6d906ead50009 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vikas Manocha77417102017-04-10 15:02:57 -07002/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha77417102017-04-10 15:02:57 -07005 */
6
7#include <common.h>
8#include <clk.h>
9#include <dm.h>
10#include <fdtdec.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Vikas Manocha77417102017-04-10 15:02:57 -070012#include <asm/arch/gpio.h>
13#include <asm/arch/stm32.h>
14#include <asm/gpio.h>
15#include <asm/io.h>
Simon Glass336d4612020-02-03 07:36:16 -070016#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060017#include <linux/bitops.h>
Vikas Manocha77417102017-04-10 15:02:57 -070018#include <linux/errno.h>
19#include <linux/io.h>
20
Patrick Delaunayf13ff882020-06-04 14:30:25 +020021#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
Vikas Manocha77417102017-04-10 15:02:57 -070022#define MODE_BITS_MASK 3
Patrick Delaunayf13ff882020-06-04 14:30:25 +020023#define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
24
25#define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
26#define PUPD_MASK 3
27
28#define OTYPE_BITS(gpio_pin) (gpio_pin)
29#define OTYPE_MSK 1
30
31static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
32 int idx,
33 int mode)
34{
35 int bits_index;
36 int mask;
37
38 bits_index = MODE_BITS(idx);
39 mask = MODE_BITS_MASK << bits_index;
40
41 clrsetbits_le32(&regs->moder, mask, mode << bits_index);
42}
43
Patrick Delaunay43efbb62020-06-04 14:30:26 +020044static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
45{
46 return (readl(&regs->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
47}
48
Patrick Delaunayf13ff882020-06-04 14:30:25 +020049static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
50 int idx,
51 enum stm32_gpio_otype otype)
52{
53 int bits;
54
55 bits = OTYPE_BITS(idx);
56 clrsetbits_le32(&regs->otyper, OTYPE_MSK << bits, otype << bits);
57}
58
Patrick Delaunay43efbb62020-06-04 14:30:26 +020059static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
60 int idx)
61{
62 return (readl(&regs->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
63}
64
Patrick Delaunayf13ff882020-06-04 14:30:25 +020065static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
66 int idx,
67 enum stm32_gpio_pupd pupd)
68{
69 int bits;
70
71 bits = PUPD_BITS(idx);
72 clrsetbits_le32(&regs->pupdr, PUPD_MASK << bits, pupd << bits);
73}
Vikas Manocha77417102017-04-10 15:02:57 -070074
Patrick Delaunay43efbb62020-06-04 14:30:26 +020075static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
76 int idx)
77{
78 return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
79}
80
Patrice Chotarddbf928d2018-12-03 10:52:51 +010081/*
82 * convert gpio offset to gpio index taking into account gpio holes
83 * into gpio bank
84 */
85int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
86{
87 struct stm32_gpio_priv *priv = dev_get_priv(dev);
Patrick Delaunay99e14b22019-06-21 15:26:46 +020088 unsigned int idx = 0;
Patrice Chotarddbf928d2018-12-03 10:52:51 +010089 int i;
90
91 for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
92 if (priv->gpio_range & BIT(i)) {
93 if (idx == offset)
94 return idx;
95 idx++;
96 }
97 }
98 /* shouldn't happen */
99 return -EINVAL;
100}
101
Vikas Manocha77417102017-04-10 15:02:57 -0700102static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
103{
104 struct stm32_gpio_priv *priv = dev_get_priv(dev);
105 struct stm32_gpio_regs *regs = priv->regs;
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100106 int idx;
107
108 idx = stm32_offset_to_index(dev, offset);
109 if (idx < 0)
110 return idx;
111
Patrick Delaunayf13ff882020-06-04 14:30:25 +0200112 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
Vikas Manocha77417102017-04-10 15:02:57 -0700113
114 return 0;
115}
116
117static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
118 int value)
119{
120 struct stm32_gpio_priv *priv = dev_get_priv(dev);
121 struct stm32_gpio_regs *regs = priv->regs;
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100122 int idx;
123
124 idx = stm32_offset_to_index(dev, offset);
125 if (idx < 0)
126 return idx;
127
Patrick Delaunayf13ff882020-06-04 14:30:25 +0200128 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
Patrice Chotard798cd702018-08-09 11:57:57 +0200129
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100130 writel(BSRR_BIT(idx, value), &regs->bsrr);
Vikas Manocha77417102017-04-10 15:02:57 -0700131
132 return 0;
133}
134
135static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
136{
137 struct stm32_gpio_priv *priv = dev_get_priv(dev);
138 struct stm32_gpio_regs *regs = priv->regs;
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100139 int idx;
Vikas Manocha77417102017-04-10 15:02:57 -0700140
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100141 idx = stm32_offset_to_index(dev, offset);
142 if (idx < 0)
143 return idx;
144
145 return readl(&regs->idr) & BIT(idx) ? 1 : 0;
Vikas Manocha77417102017-04-10 15:02:57 -0700146}
147
148static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
149{
150 struct stm32_gpio_priv *priv = dev_get_priv(dev);
151 struct stm32_gpio_regs *regs = priv->regs;
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100152 int idx;
Vikas Manocha77417102017-04-10 15:02:57 -0700153
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100154 idx = stm32_offset_to_index(dev, offset);
155 if (idx < 0)
156 return idx;
157
158 writel(BSRR_BIT(idx, value), &regs->bsrr);
Vikas Manocha77417102017-04-10 15:02:57 -0700159
160 return 0;
161}
162
Patrice Chotardcad73242018-10-24 14:10:21 +0200163static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
164{
165 struct stm32_gpio_priv *priv = dev_get_priv(dev);
166 struct stm32_gpio_regs *regs = priv->regs;
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100167 int bits_index;
168 int mask;
169 int idx;
Patrice Chotardcad73242018-10-24 14:10:21 +0200170 u32 mode;
171
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100172 idx = stm32_offset_to_index(dev, offset);
173 if (idx < 0)
174 return idx;
175
176 bits_index = MODE_BITS(idx);
177 mask = MODE_BITS_MASK << bits_index;
178
Patrice Chotardcad73242018-10-24 14:10:21 +0200179 mode = (readl(&regs->moder) & mask) >> bits_index;
180 if (mode == STM32_GPIO_MODE_OUT)
181 return GPIOF_OUTPUT;
182 if (mode == STM32_GPIO_MODE_IN)
183 return GPIOF_INPUT;
184 if (mode == STM32_GPIO_MODE_AN)
185 return GPIOF_UNUSED;
186
187 return GPIOF_FUNC;
188}
189
Patrick Delaunayf13ff882020-06-04 14:30:25 +0200190static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
191 ulong flags)
192{
193 struct stm32_gpio_priv *priv = dev_get_priv(dev);
194 struct stm32_gpio_regs *regs = priv->regs;
195 int idx;
196
197 idx = stm32_offset_to_index(dev, offset);
198 if (idx < 0)
199 return idx;
200
201 if (flags & GPIOD_IS_OUT) {
202 int value = GPIOD_FLAGS_OUTPUT(flags);
203
204 if (flags & GPIOD_OPEN_DRAIN)
205 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
206 else
207 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
208 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
209 writel(BSRR_BIT(idx, value), &regs->bsrr);
210
211 } else if (flags & GPIOD_IS_IN) {
212 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
213 if (flags & GPIOD_PULL_UP)
214 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
215 else if (flags & GPIOD_PULL_DOWN)
216 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
217 }
218
219 return 0;
220}
221
Patrick Delaunay43efbb62020-06-04 14:30:26 +0200222static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
223 ulong *flags)
224{
225 struct stm32_gpio_priv *priv = dev_get_priv(dev);
226 struct stm32_gpio_regs *regs = priv->regs;
227 int idx;
228 ulong dir_flags = 0;
229
230 idx = stm32_offset_to_index(dev, offset);
231 if (idx < 0)
232 return idx;
233
234 switch (stm32_gpio_get_moder(regs, idx)) {
235 case STM32_GPIO_MODE_OUT:
236 dir_flags |= GPIOD_IS_OUT;
237 if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
238 dir_flags |= GPIOD_OPEN_DRAIN;
239 if (readl(&regs->idr) & BIT(idx))
240 dir_flags |= GPIOD_IS_OUT_ACTIVE;
241 break;
242 case STM32_GPIO_MODE_IN:
243 dir_flags |= GPIOD_IS_IN;
244 switch (stm32_gpio_get_pupd(regs, idx)) {
245 case STM32_GPIO_PUPD_UP:
246 dir_flags |= GPIOD_PULL_UP;
247 break;
248 case STM32_GPIO_PUPD_DOWN:
249 dir_flags |= GPIOD_PULL_DOWN;
250 break;
251 default:
252 break;
253 }
254 break;
255 default:
256 break;
257 }
258 *flags = dir_flags;
259
260 return 0;
261}
262
Vikas Manocha77417102017-04-10 15:02:57 -0700263static const struct dm_gpio_ops gpio_stm32_ops = {
264 .direction_input = stm32_gpio_direction_input,
265 .direction_output = stm32_gpio_direction_output,
266 .get_value = stm32_gpio_get_value,
267 .set_value = stm32_gpio_set_value,
Patrice Chotardcad73242018-10-24 14:10:21 +0200268 .get_function = stm32_gpio_get_function,
Patrick Delaunayf13ff882020-06-04 14:30:25 +0200269 .set_dir_flags = stm32_gpio_set_dir_flags,
Patrick Delaunay43efbb62020-06-04 14:30:26 +0200270 .get_dir_flags = stm32_gpio_get_dir_flags,
Vikas Manocha77417102017-04-10 15:02:57 -0700271};
272
273static int gpio_stm32_probe(struct udevice *dev)
274{
Vikas Manocha77417102017-04-10 15:02:57 -0700275 struct stm32_gpio_priv *priv = dev_get_priv(dev);
Patrick Delaunay15c8cbf2020-09-09 18:28:33 +0200276 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
277 struct ofnode_phandle_args args;
278 const char *name;
Patrice Chotard8b6d45a2018-12-03 10:52:53 +0100279 struct clk clk;
Vikas Manocha77417102017-04-10 15:02:57 -0700280 fdt_addr_t addr;
Patrick Delaunay15c8cbf2020-09-09 18:28:33 +0200281 int ret, i;
Vikas Manocha77417102017-04-10 15:02:57 -0700282
Patrick Delaunayd876eaf2018-03-12 10:46:07 +0100283 addr = dev_read_addr(dev);
Vikas Manocha77417102017-04-10 15:02:57 -0700284 if (addr == FDT_ADDR_T_NONE)
285 return -EINVAL;
286
287 priv->regs = (struct stm32_gpio_regs *)addr;
Patrice Chotard4fb22462019-01-04 10:55:06 +0100288
Patrick Delaunayd876eaf2018-03-12 10:46:07 +0100289 name = dev_read_string(dev, "st,bank-name");
Vikas Manocha77417102017-04-10 15:02:57 -0700290 if (!name)
291 return -EINVAL;
292 uc_priv->bank_name = name;
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100293
294 i = 0;
295 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
296 NULL, 3, i, &args);
297
Patrick Delaunaycb08e842020-09-09 18:28:34 +0200298 if (!ret && args.args_count < 3)
299 return -EINVAL;
300
Patrice Chotard39a8f0b2019-01-04 10:55:05 +0100301 if (ret == -ENOENT) {
302 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
303 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
304 }
305
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100306 while (ret != -ENOENT) {
307 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
308 args.args[0]);
309
310 uc_priv->gpio_count += args.args[2];
311
312 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
313 ++i, &args);
Patrick Delaunaycb08e842020-09-09 18:28:34 +0200314 if (!ret && args.args_count < 3)
315 return -EINVAL;
Patrice Chotarddbf928d2018-12-03 10:52:51 +0100316 }
317
318 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
319 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
320 priv->gpio_range);
Patrick Delaunayf17412e2020-04-22 14:29:17 +0200321
Vikas Manocha77417102017-04-10 15:02:57 -0700322 ret = clk_get_by_index(dev, 0, &clk);
323 if (ret < 0)
324 return ret;
325
326 ret = clk_enable(&clk);
327
328 if (ret) {
329 dev_err(dev, "failed to enable clock\n");
330 return ret;
331 }
332 debug("clock enabled for device %s\n", dev->name);
Vikas Manocha77417102017-04-10 15:02:57 -0700333
334 return 0;
335}
336
Vikas Manocha77417102017-04-10 15:02:57 -0700337U_BOOT_DRIVER(gpio_stm32) = {
338 .name = "gpio_stm32",
339 .id = UCLASS_GPIO,
Vikas Manocha77417102017-04-10 15:02:57 -0700340 .probe = gpio_stm32_probe,
341 .ops = &gpio_stm32_ops,
Bin Meng695c4992018-10-24 06:36:30 -0700342 .flags = DM_UC_FLAG_SEQ_ALIAS,
Vikas Manocha77417102017-04-10 15:02:57 -0700343 .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
344};