blob: a849f7b199736eb2ba445b1c490f1238e6703172 [file] [log] [blame]
Stefan Roese10e8bf82014-11-07 12:37:49 +01001/*
2 * Copyright (C) 2012
3 * Altera Corporation <www.altera.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CADENCE_QSPI_H__
9#define __CADENCE_QSPI_H__
10
11#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
12
13#define CQSPI_NO_DECODER_MAX_CS 4
14#define CQSPI_DECODER_MAX_CS 16
15#define CQSPI_READ_CAPTURE_MAX_DELAY 16
16
17struct cadence_spi_platdata {
18 unsigned int max_hz;
19 void *regbase;
20 void *ahbbase;
21
22 u32 page_size;
23 u32 block_size;
24 u32 tshsl_ns;
25 u32 tsd2d_ns;
26 u32 tchsh_ns;
27 u32 tslch_ns;
Vikas Manocha90a2f712015-07-02 18:29:44 -070028 u32 sram_size;
Stefan Roese10e8bf82014-11-07 12:37:49 +010029};
30
31struct cadence_spi_priv {
32 void *regbase;
33 void *ahbbase;
34 size_t cmd_len;
35 u8 cmd_buf[32];
36 size_t data_len;
37
38 int qspi_is_init;
39 unsigned int qspi_calibrated_hz;
40 unsigned int qspi_calibrated_cs;
Chin Liang See98fbd712015-10-17 08:31:55 -050041 unsigned int previous_hz;
Stefan Roese10e8bf82014-11-07 12:37:49 +010042};
43
44/* Functions call declaration */
45void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
46void cadence_qspi_apb_controller_enable(void *reg_base_addr);
47void cadence_qspi_apb_controller_disable(void *reg_base_addr);
48
49int cadence_qspi_apb_command_read(void *reg_base_addr,
50 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
51int cadence_qspi_apb_command_write(void *reg_base_addr,
52 unsigned int cmdlen, const u8 *cmdbuf,
53 unsigned int txlen, const u8 *txbuf);
54
55int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
Vignesh R2372e142016-07-06 10:20:56 +053056 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
Stefan Roese10e8bf82014-11-07 12:37:49 +010057int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
58 unsigned int rxlen, u8 *rxbuf);
59int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
60 unsigned int cmdlen, const u8 *cmdbuf);
61int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
62 unsigned int txlen, const u8 *txbuf);
63
64void cadence_qspi_apb_chipselect(void *reg_base,
65 unsigned int chip_select, unsigned int decoder_enable);
66void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
67 unsigned int clk_pol, unsigned int clk_pha);
68void cadence_qspi_apb_config_baudrate_div(void *reg_base,
69 unsigned int ref_clk_hz, unsigned int sclk_hz);
70void cadence_qspi_apb_delay(void *reg_base,
71 unsigned int ref_clk, unsigned int sclk_hz,
72 unsigned int tshsl_ns, unsigned int tsd2d_ns,
73 unsigned int tchsh_ns, unsigned int tslch_ns);
74void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
75void cadence_qspi_apb_readdata_capture(void *reg_base,
76 unsigned int bypass, unsigned int delay);
77
78#endif /* __CADENCE_QSPI_H__ */