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Michael Schwingen81b20cc2007-12-07 23:35:02 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, <michael@schwingen.org>
4 *
5 * based in great part on jedec_probe.c from linux kernel:
6 * (C) 2000 Red Hat. GPL'd.
7 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 */
28
29/* The DEBUG define must be before common to enable debugging */
30/*#define DEBUG*/
31
32#include <common.h>
33#include <asm/processor.h>
34#include <asm/io.h>
35#include <asm/byteorder.h>
36#include <environment.h>
37
38#define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
39
Michael Schwingen81b20cc2007-12-07 23:35:02 +010040/* AMD */
Stefan Roese0192d7d2008-07-08 12:57:14 +020041#define AM29DL800BB 0x22CB
Michael Schwingen81b20cc2007-12-07 23:35:02 +010042#define AM29DL800BT 0x224A
43
44#define AM29F800BB 0x2258
45#define AM29F800BT 0x22D6
46#define AM29LV400BB 0x22BA
47#define AM29LV400BT 0x22B9
48#define AM29LV800BB 0x225B
49#define AM29LV800BT 0x22DA
50#define AM29LV160DT 0x22C4
51#define AM29LV160DB 0x2249
52#define AM29F017D 0x003D
53#define AM29F016D 0x00AD
54#define AM29F080 0x00D5
55#define AM29F040 0x00A4
56#define AM29LV040B 0x004F
57#define AM29F032B 0x0041
58#define AM29F002T 0x00B0
59
60/* SST */
61#define SST39LF800 0x2781
62#define SST39LF160 0x2782
63#define SST39VF1601 0x234b
64#define SST39LF512 0x00D4
65#define SST39LF010 0x00D5
66#define SST39LF020 0x00D6
67#define SST39LF040 0x00D7
68#define SST39SF010A 0x00B5
69#define SST39SF020A 0x00B6
70
Niklaus Giger3a7b2c22009-07-22 17:13:24 +020071/* MXIC */
72#define MX29LV040 0x004F
73
74/* WINBOND */
75#define W39L040A 0x00D6
76
77/* AMIC */
78#define A29L040 0x0092
79
80/* EON */
81#define EN29LV040A 0x004F
Michael Schwingen81b20cc2007-12-07 23:35:02 +010082
83/*
84 * Unlock address sets for AMD command sets.
85 * Intel command sets use the MTD_UADDR_UNNECESSARY.
86 * Each identifier, except MTD_UADDR_UNNECESSARY, and
87 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
88 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
89 * initialization need not require initializing all of the
90 * unlock addresses for all bit widths.
91 */
92enum uaddr {
93 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
94 MTD_UADDR_0x0555_0x02AA,
95 MTD_UADDR_0x0555_0x0AAA,
96 MTD_UADDR_0x5555_0x2AAA,
97 MTD_UADDR_0x0AAA_0x0555,
98 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
99 MTD_UADDR_UNNECESSARY, /* Does not require any address */
100};
101
102
103struct unlock_addr {
104 u32 addr1;
105 u32 addr2;
106};
107
108
109/*
110 * I don't like the fact that the first entry in unlock_addrs[]
111 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
112 * should not be used. The problem is that structures with
113 * initializers have extra fields initialized to 0. It is _very_
114 * desireable to have the unlock address entries for unsupported
115 * data widths automatically initialized - that means that
116 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
117 * must go unused.
118 */
119static const struct unlock_addr unlock_addrs[] = {
120 [MTD_UADDR_NOT_SUPPORTED] = {
121 .addr1 = 0xffff,
122 .addr2 = 0xffff
123 },
124
125 [MTD_UADDR_0x0555_0x02AA] = {
126 .addr1 = 0x0555,
127 .addr2 = 0x02aa
128 },
129
130 [MTD_UADDR_0x0555_0x0AAA] = {
131 .addr1 = 0x0555,
132 .addr2 = 0x0aaa
133 },
134
135 [MTD_UADDR_0x5555_0x2AAA] = {
136 .addr1 = 0x5555,
137 .addr2 = 0x2aaa
138 },
139
140 [MTD_UADDR_0x0AAA_0x0555] = {
141 .addr1 = 0x0AAA,
142 .addr2 = 0x0555
143 },
144
145 [MTD_UADDR_DONT_CARE] = {
146 .addr1 = 0x0000, /* Doesn't matter which address */
147 .addr2 = 0x0000 /* is used - must be last entry */
148 },
149
150 [MTD_UADDR_UNNECESSARY] = {
151 .addr1 = 0x0000,
152 .addr2 = 0x0000
153 }
154};
155
156
157struct amd_flash_info {
158 const __u16 mfr_id;
159 const __u16 dev_id;
160 const char *name;
161 const int DevSize;
162 const int NumEraseRegions;
163 const int CmdSet;
164 const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
165 const ulong regions[6];
166};
167
168#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
169
170#define SIZE_64KiB 16
171#define SIZE_128KiB 17
172#define SIZE_256KiB 18
173#define SIZE_512KiB 19
174#define SIZE_1MiB 20
175#define SIZE_2MiB 21
176#define SIZE_4MiB 22
177#define SIZE_8MiB 23
178
179static const struct amd_flash_info jedec_table[] = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100181 {
Stefan Roese28745db2009-01-29 11:21:38 +0100182 .mfr_id = (u16)SST_MANUFACT,
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100183 .dev_id = SST39LF020,
184 .name = "SST 39LF020",
Stefan Roese9692c272007-12-08 08:25:09 +0100185 .uaddr = {
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100186 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
187 },
188 .DevSize = SIZE_256KiB,
189 .CmdSet = P_ID_AMD_STD,
190 .NumEraseRegions= 1,
191 .regions = {
192 ERASEINFO(0x01000,64),
193 }
Stefan Roese9692c272007-12-08 08:25:09 +0100194 },
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100195#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100197 {
Stefan Roese28745db2009-01-29 11:21:38 +0100198 .mfr_id = (u16)AMD_MANUFACT,
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100199 .dev_id = AM29LV040B,
200 .name = "AMD AM29LV040B",
201 .uaddr = {
202 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
203 },
204 .DevSize = SIZE_512KiB,
205 .CmdSet = P_ID_AMD_STD,
206 .NumEraseRegions= 1,
207 .regions = {
208 ERASEINFO(0x10000,8),
209 }
210 },
211 {
Stefan Roese28745db2009-01-29 11:21:38 +0100212 .mfr_id = (u16)SST_MANUFACT,
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100213 .dev_id = SST39LF040,
214 .name = "SST 39LF040",
Stefan Roese9692c272007-12-08 08:25:09 +0100215 .uaddr = {
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100216 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
217 },
218 .DevSize = SIZE_512KiB,
219 .CmdSet = P_ID_AMD_STD,
220 .NumEraseRegions= 1,
221 .regions = {
222 ERASEINFO(0x01000,128),
223 }
Stefan Roese9692c272007-12-08 08:25:09 +0100224 },
Niklaus Giger94f92792008-12-08 17:24:08 +0100225 {
Stefan Roese28745db2009-01-29 11:21:38 +0100226 .mfr_id = (u16)STM_MANUFACT,
Niklaus Giger94f92792008-12-08 17:24:08 +0100227 .dev_id = STM_ID_M29W040B,
228 .name = "ST Micro M29W040B",
229 .uaddr = {
230 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
231 },
232 .DevSize = SIZE_512KiB,
233 .CmdSet = P_ID_AMD_STD,
234 .NumEraseRegions= 1,
235 .regions = {
236 ERASEINFO(0x10000,8),
237 }
238 },
Niklaus Giger3a7b2c22009-07-22 17:13:24 +0200239 {
240 .mfr_id = (u16)MX_MANUFACT,
241 .dev_id = MX29LV040,
242 .name = "MXIC MX29LV040",
243 .uaddr = {
244 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
245 },
246 .DevSize = SIZE_512KiB,
247 .CmdSet = P_ID_AMD_STD,
248 .NumEraseRegions= 1,
249 .regions = {
250 ERASEINFO(0x10000, 8),
251 }
252 },
253 {
254 .mfr_id = (u16)WINB_MANUFACT,
255 .dev_id = W39L040A,
256 .name = "WINBOND W39L040A",
257 .uaddr = {
258 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
259 },
260 .DevSize = SIZE_512KiB,
261 .CmdSet = P_ID_AMD_STD,
262 .NumEraseRegions= 1,
263 .regions = {
264 ERASEINFO(0x10000, 8),
265 }
266 },
267 {
268 .mfr_id = (u16)AMIC_MANUFACT,
269 .dev_id = A29L040,
270 .name = "AMIC A29L040",
271 .uaddr = {
272 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
273 },
274 .DevSize = SIZE_512KiB,
275 .CmdSet = P_ID_AMD_STD,
276 .NumEraseRegions= 1,
277 .regions = {
278 ERASEINFO(0x10000, 8),
279 }
280 },
281 {
282 .mfr_id = (u16)EON_MANUFACT,
283 .dev_id = EN29LV040A,
284 .name = "EON EN29LV040A",
285 .uaddr = {
286 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
287 },
288 .DevSize = SIZE_512KiB,
289 .CmdSet = P_ID_AMD_STD,
290 .NumEraseRegions= 1,
291 .regions = {
292 ERASEINFO(0x10000, 8),
293 }
294 },
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100295#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
Tor Krill90447ec2008-03-28 11:29:10 +0100297 {
Stefan Roese28745db2009-01-29 11:21:38 +0100298 .mfr_id = (u16)AMD_MANUFACT,
Tor Krill90447ec2008-03-28 11:29:10 +0100299 .dev_id = AM29LV400BB,
300 .name = "AMD AM29LV400BB",
301 .uaddr = {
302 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
303 },
304 .DevSize = SIZE_512KiB,
305 .CmdSet = CFI_CMDSET_AMD_LEGACY,
306 .NumEraseRegions= 4,
307 .regions = {
308 ERASEINFO(0x04000,1),
309 ERASEINFO(0x02000,2),
310 ERASEINFO(0x08000,1),
311 ERASEINFO(0x10000,7),
312 }
313 },
Guennadi Liakhovetski79498392008-08-05 15:36:39 +0200314 {
Stefan Roese28745db2009-01-29 11:21:38 +0100315 .mfr_id = (u16)AMD_MANUFACT,
Guennadi Liakhovetski79498392008-08-05 15:36:39 +0200316 .dev_id = AM29LV800BB,
317 .name = "AMD AM29LV800BB",
318 .uaddr = {
319 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
320 },
321 .DevSize = SIZE_1MiB,
322 .CmdSet = CFI_CMDSET_AMD_LEGACY,
323 .NumEraseRegions= 4,
324 .regions = {
325 ERASEINFO(0x04000, 1),
326 ERASEINFO(0x02000, 2),
327 ERASEINFO(0x08000, 1),
328 ERASEINFO(0x10000, 15),
329 }
330 },
Tor Krill90447ec2008-03-28 11:29:10 +0100331#endif
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100332};
333
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100334static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
335{
336 int i,j;
337 int sect_cnt;
338 int size_ratio;
339 int total_size;
340 enum uaddr uaddr_idx;
341
342 size_ratio = info->portwidth / info->chipwidth;
343
344 debug("Found JEDEC Flash: %s\n", jedec_entry->name);
345 info->vendor = jedec_entry->CmdSet;
346 /* Todo: do we need device-specific timeouts? */
347 info->erase_blk_tout = 30000;
348 info->buffer_write_tout = 1000;
349 info->write_tout = 100;
350 info->name = jedec_entry->name;
351
352 /* copy unlock addresses from device table to CFI info struct. This
353 is just here because the addresses are in the table anyway - if
354 the flash is not detected due to wrong unlock addresses,
355 flash_detect_legacy would have to try all of them before we even
356 get here. */
357 switch(info->chipwidth) {
358 case FLASH_CFI_8BIT:
359 uaddr_idx = jedec_entry->uaddr[0];
360 break;
361 case FLASH_CFI_16BIT:
362 uaddr_idx = jedec_entry->uaddr[1];
363 break;
364 case FLASH_CFI_32BIT:
365 uaddr_idx = jedec_entry->uaddr[2];
366 break;
367 default:
368 uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
369 break;
370 }
371
372 debug("unlock address index %d\n", uaddr_idx);
373 info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
374 info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
375 debug("unlock addresses are 0x%x/0x%x\n", info->addr_unlock1, info->addr_unlock2);
376
377 sect_cnt = 0;
378 total_size = 0;
379 for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
380 ulong erase_region_size = jedec_entry->regions[i] >> 8;
381 ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
382
383 total_size += erase_region_size * erase_region_count;
384 debug ("erase_region_count = %d erase_region_size = %d\n",
385 erase_region_count, erase_region_size);
386 for (j = 0; j < erase_region_count; j++) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100388 printf("ERROR: too many flash sectors\n");
389 break;
390 }
391 info->start[sect_cnt] = base;
392 base += (erase_region_size * size_ratio);
393 sect_cnt++;
394 }
395 }
396 info->sector_count = sect_cnt;
397 info->size = total_size * size_ratio;
398}
399
400/*-----------------------------------------------------------------------
401 * match jedec ids against table. If a match is found, fill flash_info entry
402 */
403int jedec_flash_match(flash_info_t *info, ulong base)
404{
405 int ret = 0;
406 int i;
407 ulong mask = 0xFFFF;
408 if (info->chipwidth == 1)
409 mask = 0xFF;
410
411 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
412 if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
413 (jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
414 fill_info(info, &jedec_table[i], base);
415 ret = 1;
416 break;
417 }
418 }
419 return ret;
420}