Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2015 - 2016 Xilinx, Inc. |
Michal Simek | 174d7284 | 2023-07-10 14:35:49 +0200 | [diff] [blame] | 4 | * Michal Simek <michal.simek@amd.com> |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 5 | */ |
| 6 | #include <common.h> |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 7 | #include <dm.h> |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 8 | #include <ahci.h> |
Michal Simek | f6f5451 | 2022-02-07 10:36:33 +0100 | [diff] [blame] | 9 | #include <generic-phy.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Michal Simek | f6f5451 | 2022-02-07 10:36:33 +0100 | [diff] [blame] | 11 | #include <reset.h> |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 12 | #include <scsi.h> |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 13 | #include <asm/io.h> |
Michal Simek | f6f5451 | 2022-02-07 10:36:33 +0100 | [diff] [blame] | 14 | #include <dm/device_compat.h> |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 15 | #include <linux/ioport.h> |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 16 | |
| 17 | /* Vendor Specific Register Offsets */ |
| 18 | #define AHCI_VEND_PCFG 0xA4 |
| 19 | #define AHCI_VEND_PPCFG 0xA8 |
| 20 | #define AHCI_VEND_PP2C 0xAC |
| 21 | #define AHCI_VEND_PP3C 0xB0 |
| 22 | #define AHCI_VEND_PP4C 0xB4 |
| 23 | #define AHCI_VEND_PP5C 0xB8 |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 24 | #define AHCI_VEND_AXICC 0xBc |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 25 | #define AHCI_VEND_PAXIC 0xC0 |
| 26 | #define AHCI_VEND_PTC 0xC8 |
| 27 | |
| 28 | /* Vendor Specific Register bit definitions */ |
| 29 | #define PAXIC_ADBW_BW64 0x1 |
| 30 | #define PAXIC_MAWIDD (1 << 8) |
| 31 | #define PAXIC_MARIDD (1 << 16) |
| 32 | #define PAXIC_OTL (0x4 << 20) |
| 33 | |
| 34 | #define PCFG_TPSS_VAL (0x32 << 16) |
| 35 | #define PCFG_TPRS_VAL (0x2 << 12) |
| 36 | #define PCFG_PAD_VAL 0x2 |
| 37 | |
| 38 | #define PPCFG_TTA 0x1FFFE |
| 39 | #define PPCFG_PSSO_EN (1 << 28) |
| 40 | #define PPCFG_PSS_EN (1 << 29) |
| 41 | #define PPCFG_ESDF_EN (1 << 31) |
| 42 | |
| 43 | #define PP2C_CIBGMN 0x0F |
| 44 | #define PP2C_CIBGMX (0x25 << 8) |
| 45 | #define PP2C_CIBGN (0x18 << 16) |
| 46 | #define PP2C_CINMP (0x29 << 24) |
| 47 | |
| 48 | #define PP3C_CWBGMN 0x04 |
| 49 | #define PP3C_CWBGMX (0x0B << 8) |
| 50 | #define PP3C_CWBGN (0x08 << 16) |
| 51 | #define PP3C_CWNMP (0x0F << 24) |
| 52 | |
| 53 | #define PP4C_BMX 0x0a |
| 54 | #define PP4C_BNM (0x08 << 8) |
| 55 | #define PP4C_SFD (0x4a << 16) |
| 56 | #define PP4C_PTST (0x06 << 24) |
| 57 | |
| 58 | #define PP5C_RIT 0x60216 |
| 59 | #define PP5C_RCT (0x7f0 << 20) |
| 60 | |
| 61 | #define PTC_RX_WM_VAL 0x40 |
| 62 | #define PTC_RSVD (1 << 27) |
| 63 | |
| 64 | #define PORT0_BASE 0x100 |
| 65 | #define PORT1_BASE 0x180 |
| 66 | |
| 67 | /* Port Control Register Bit Definitions */ |
| 68 | #define PORT_SCTL_SPD_GEN3 (0x3 << 4) |
| 69 | #define PORT_SCTL_SPD_GEN2 (0x2 << 4) |
| 70 | #define PORT_SCTL_SPD_GEN1 (0x1 << 4) |
| 71 | #define PORT_SCTL_IPM (0x3 << 8) |
| 72 | |
| 73 | #define PORT_BASE 0x100 |
| 74 | #define PORT_OFFSET 0x80 |
| 75 | #define NR_PORTS 2 |
| 76 | #define DRV_NAME "ahci-ceva" |
| 77 | #define CEVA_FLAG_BROKEN_GEN2 1 |
| 78 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 79 | /* flag bit definition */ |
| 80 | #define FLAG_COHERENT 1 |
| 81 | |
| 82 | /* register config value */ |
| 83 | #define CEVA_PHY1_CFG 0xa003fffe |
| 84 | #define CEVA_PHY2_CFG 0x28184d1f |
| 85 | #define CEVA_PHY3_CFG 0x0e081509 |
| 86 | #define CEVA_TRANS_CFG 0x08000029 |
| 87 | #define CEVA_AXICC_CFG 0x3fffffff |
| 88 | |
Peng Ma | df983a7 | 2018-08-01 14:15:43 +0800 | [diff] [blame] | 89 | /* for ls1021a */ |
Peng Ma | aaaffe9 | 2018-10-22 10:39:49 +0800 | [diff] [blame] | 90 | #define LS1021_AHCI_VEND_AXICC 0xC0 |
Peng Ma | df983a7 | 2018-08-01 14:15:43 +0800 | [diff] [blame] | 91 | #define LS1021_CEVA_PHY2_CFG 0x28183414 |
| 92 | #define LS1021_CEVA_PHY3_CFG 0x0e080e06 |
| 93 | #define LS1021_CEVA_PHY4_CFG 0x064a080b |
| 94 | #define LS1021_CEVA_PHY5_CFG 0x2aa86470 |
| 95 | |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 96 | /* ecc val pair */ |
| 97 | #define ECC_DIS_VAL_CH1 0x00020000 |
Peng Ma | aaaffe9 | 2018-10-22 10:39:49 +0800 | [diff] [blame] | 98 | #define ECC_DIS_VAL_CH2 0x80000000 |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 99 | #define ECC_DIS_VAL_CH3 0x40000000 |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 100 | |
| 101 | enum ceva_soc { |
| 102 | CEVA_1V84, |
| 103 | CEVA_LS1012A, |
Peng Ma | df983a7 | 2018-08-01 14:15:43 +0800 | [diff] [blame] | 104 | CEVA_LS1021A, |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 105 | CEVA_LS1028A, |
Peng Ma | 822d060 | 2018-08-01 11:35:15 +0800 | [diff] [blame] | 106 | CEVA_LS1043A, |
Peng Ma | 5fcae59 | 2018-10-11 10:34:19 +0000 | [diff] [blame] | 107 | CEVA_LS1046A, |
Peng Ma | aaaffe9 | 2018-10-22 10:39:49 +0800 | [diff] [blame] | 108 | CEVA_LS1088A, |
Peng Ma | 1039d1a | 2018-10-22 10:43:20 +0800 | [diff] [blame] | 109 | CEVA_LS2080A, |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 110 | }; |
| 111 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 112 | struct ceva_sata_priv { |
| 113 | ulong base; |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 114 | ulong ecc_base; |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 115 | enum ceva_soc soc; |
| 116 | ulong flag; |
| 117 | }; |
| 118 | |
| 119 | static int ceva_init_sata(struct ceva_sata_priv *priv) |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 120 | { |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 121 | ulong ecc_addr = priv->ecc_base; |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 122 | ulong base = priv->base; |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 123 | ulong tmp; |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 124 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 125 | switch (priv->soc) { |
| 126 | case CEVA_1V84: |
| 127 | tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; |
| 128 | writel(tmp, base + AHCI_VEND_PAXIC); |
| 129 | tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL; |
| 130 | writel(tmp, base + AHCI_VEND_PCFG); |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 131 | tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 132 | writel(tmp, base + AHCI_VEND_PPCFG); |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 133 | tmp = PTC_RX_WM_VAL | PTC_RSVD; |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 134 | writel(tmp, base + AHCI_VEND_PTC); |
| 135 | break; |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 136 | |
Peng Ma | df983a7 | 2018-08-01 14:15:43 +0800 | [diff] [blame] | 137 | case CEVA_LS1021A: |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 138 | if (!ecc_addr) |
| 139 | return -EINVAL; |
| 140 | writel(ECC_DIS_VAL_CH1, ecc_addr); |
Peng Ma | df983a7 | 2018-08-01 14:15:43 +0800 | [diff] [blame] | 141 | writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); |
| 142 | writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C); |
| 143 | writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C); |
| 144 | writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C); |
| 145 | writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C); |
| 146 | writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); |
Peng Ma | df983a7 | 2018-08-01 14:15:43 +0800 | [diff] [blame] | 147 | break; |
| 148 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 149 | case CEVA_LS1012A: |
Peng Ma | 822d060 | 2018-08-01 11:35:15 +0800 | [diff] [blame] | 150 | case CEVA_LS1043A: |
Peng Ma | 5fcae59 | 2018-10-11 10:34:19 +0000 | [diff] [blame] | 151 | case CEVA_LS1046A: |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 152 | if (!ecc_addr) |
| 153 | return -EINVAL; |
| 154 | writel(ECC_DIS_VAL_CH2, ecc_addr); |
Peng Ma | 1039d1a | 2018-10-22 10:43:20 +0800 | [diff] [blame] | 155 | /* fallthrough */ |
| 156 | case CEVA_LS2080A: |
Peng Ma | aaaffe9 | 2018-10-22 10:39:49 +0800 | [diff] [blame] | 157 | writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); |
| 158 | writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); |
Peng Ma | aaaffe9 | 2018-10-22 10:39:49 +0800 | [diff] [blame] | 159 | break; |
| 160 | |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 161 | case CEVA_LS1028A: |
Peng Ma | aaaffe9 | 2018-10-22 10:39:49 +0800 | [diff] [blame] | 162 | case CEVA_LS1088A: |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 163 | if (!ecc_addr) |
| 164 | return -EINVAL; |
| 165 | writel(ECC_DIS_VAL_CH3, ecc_addr); |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 166 | writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); |
| 167 | writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 168 | break; |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 169 | } |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 170 | |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 171 | if (priv->flag & FLAG_COHERENT) |
| 172 | writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); |
| 173 | |
Michal Simek | 679b994 | 2015-09-30 17:26:55 +0200 | [diff] [blame] | 174 | return 0; |
| 175 | } |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 176 | |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 177 | static int sata_ceva_bind(struct udevice *dev) |
| 178 | { |
| 179 | struct udevice *scsi_dev; |
| 180 | |
| 181 | return ahci_bind_scsi(dev, &scsi_dev); |
| 182 | } |
| 183 | |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 184 | static int sata_ceva_probe(struct udevice *dev) |
| 185 | { |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 186 | struct ceva_sata_priv *priv = dev_get_priv(dev); |
Michal Simek | f6f5451 | 2022-02-07 10:36:33 +0100 | [diff] [blame] | 187 | struct phy phy; |
| 188 | int ret; |
| 189 | struct reset_ctl_bulk resets; |
| 190 | |
| 191 | ret = generic_phy_get_by_index(dev, 0, &phy); |
| 192 | if (!ret) { |
| 193 | dev_dbg(dev, "Perform PHY initialization\n"); |
| 194 | ret = generic_phy_init(&phy); |
| 195 | if (ret) |
| 196 | return ret; |
| 197 | } else if (ret != -ENOENT) { |
| 198 | dev_dbg(dev, "could not get phy (err %d)\n", ret); |
| 199 | return ret; |
| 200 | } |
| 201 | |
| 202 | /* reset is optional */ |
| 203 | ret = reset_get_bulk(dev, &resets); |
| 204 | if (ret && ret != -ENOTSUPP && ret != -ENOENT) { |
| 205 | dev_dbg(dev, "Getting reset fails (err %d)\n", ret); |
| 206 | return ret; |
| 207 | } |
| 208 | |
| 209 | /* Just trigger reset when reset is specified */ |
| 210 | if (!ret) { |
| 211 | dev_dbg(dev, "Perform IP reset\n"); |
| 212 | ret = reset_deassert_bulk(&resets); |
| 213 | if (ret) { |
| 214 | dev_dbg(dev, "Reset fails (err %d)\n", ret); |
| 215 | reset_release_bulk(&resets); |
| 216 | return ret; |
| 217 | } |
| 218 | } |
| 219 | |
Jonas Karlman | 017ae49 | 2023-08-31 22:16:37 +0000 | [diff] [blame] | 220 | if (generic_phy_valid(&phy)) { |
Michal Simek | f6f5451 | 2022-02-07 10:36:33 +0100 | [diff] [blame] | 221 | dev_dbg(dev, "Perform PHY power on\n"); |
| 222 | ret = generic_phy_power_on(&phy); |
| 223 | if (ret) { |
| 224 | dev_dbg(dev, "PHY power on failed (err %d)\n", ret); |
| 225 | return ret; |
| 226 | } |
| 227 | } |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 228 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 229 | ceva_init_sata(priv); |
Simon Glass | 7cf1afc | 2017-06-14 21:28:37 -0600 | [diff] [blame] | 230 | |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 231 | return ahci_probe_scsi(dev, priv->base); |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | static const struct udevice_id sata_ceva_ids[] = { |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 235 | { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 }, |
| 236 | { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, |
Peng Ma | df983a7 | 2018-08-01 14:15:43 +0800 | [diff] [blame] | 237 | { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 238 | { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A }, |
Peng Ma | 822d060 | 2018-08-01 11:35:15 +0800 | [diff] [blame] | 239 | { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, |
Peng Ma | 5fcae59 | 2018-10-11 10:34:19 +0000 | [diff] [blame] | 240 | { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, |
Peng Ma | aaaffe9 | 2018-10-22 10:39:49 +0800 | [diff] [blame] | 241 | { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A }, |
Peng Ma | 1039d1a | 2018-10-22 10:43:20 +0800 | [diff] [blame] | 242 | { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A }, |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 243 | { } |
| 244 | }; |
| 245 | |
Simon Glass | d1998a9 | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 246 | static int sata_ceva_of_to_plat(struct udevice *dev) |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 247 | { |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 248 | struct ceva_sata_priv *priv = dev_get_priv(dev); |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 249 | struct resource res_regs; |
| 250 | int ret; |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 251 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 252 | if (dev_read_bool(dev, "dma-coherent")) |
| 253 | priv->flag |= FLAG_COHERENT; |
| 254 | |
| 255 | priv->base = dev_read_addr(dev); |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 256 | if (priv->base == FDT_ADDR_T_NONE) |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 257 | return -EINVAL; |
| 258 | |
Michael Walle | cde9b14 | 2021-10-13 18:14:20 +0200 | [diff] [blame] | 259 | ret = dev_read_resource_byname(dev, "sata-ecc", &res_regs); |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 260 | if (ret) |
| 261 | priv->ecc_base = 0; |
| 262 | else |
| 263 | priv->ecc_base = res_regs.start; |
| 264 | |
Yuantian Tang | 79ed61e | 2018-07-13 17:25:30 +0800 | [diff] [blame] | 265 | priv->soc = dev_get_driver_data(dev); |
| 266 | |
Peng Ma | d2ebc38 | 2019-04-17 10:10:50 +0000 | [diff] [blame] | 267 | debug("ccsr-sata-base %lx\t ecc-base %lx\n", |
| 268 | priv->base, |
| 269 | priv->ecc_base); |
| 270 | |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 271 | return 0; |
| 272 | } |
| 273 | |
| 274 | U_BOOT_DRIVER(ceva_host_blk) = { |
| 275 | .name = "ceva_sata", |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 276 | .id = UCLASS_AHCI, |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 277 | .of_match = sata_ceva_ids, |
Michal Simek | c3898a8 | 2018-04-06 13:32:52 +0200 | [diff] [blame] | 278 | .bind = sata_ceva_bind, |
Simon Glass | f6ab5a9 | 2017-06-14 21:28:43 -0600 | [diff] [blame] | 279 | .ops = &scsi_ops, |
Simon Glass | 41575d8 | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 280 | .priv_auto = sizeof(struct ceva_sata_priv), |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 281 | .probe = sata_ceva_probe, |
Simon Glass | d1998a9 | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 282 | .of_to_plat = sata_ceva_of_to_plat, |
Michal Simek | 49c4c78 | 2016-09-08 15:06:22 +0200 | [diff] [blame] | 283 | }; |