blob: 704bf03164a42d6800a952293a4852ff29c16f99 [file] [log] [blame]
wdenk03f5c552004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
wdenk03f5c552004-10-10 21:21:55 +000023#include <common.h>
24#include <pci.h>
25#include <asm/processor.h>
26#include <asm/immap_85xx.h>
Wolfgang Denk2d5df632005-07-21 16:14:36 +020027#include <ioports.h>
wdenk03f5c552004-10-10 21:21:55 +000028#include <spd.h>
29
30#include "../common/cadmus.h"
31#include "../common/eeprom.h"
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -050032#include "../common/via.h"
wdenk03f5c552004-10-10 21:21:55 +000033
Jon Loeligerd9b94f22005-07-25 14:05:07 -050034#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk03f5c552004-10-10 21:21:55 +000035extern void ddr_enable_ecc(unsigned int dram_size);
36#endif
37
38extern long int spd_sdram(void);
39
40void local_bus_init(void);
41void sdram_init(void);
42
Wolfgang Denk2d5df632005-07-21 16:14:36 +020043/*
44 * I/O Port configuration table
45 *
46 * if conf is 1, then that port pin will be configured at boot time
47 * according to the five values podr/pdir/ppar/psor/pdat for that entry
48 */
49
50const iop_conf_t iop_conf_tab[4][32] = {
51
52 /* Port A configuration */
53 { /* conf ppar psor pdir podr pdat */
54 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
55 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
56 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
57 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
58 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
59 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
60 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
61 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
62 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
63 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
64 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
65 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
66 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
67 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
68 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
69 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
70 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
71 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
72 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
73 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
74 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
75 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
76 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
77 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
78 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
79 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
80 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
81 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
82 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
83 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
84 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
85 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
86 },
87
88 /* Port B configuration */
89 { /* conf ppar psor pdir podr pdat */
90 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
91 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
92 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
93 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
94 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
95 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
96 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
97 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
98 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
99 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
100 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
101 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
102 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
103 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
104 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
105 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
106 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
107 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
108 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
109 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
110 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
122 },
123
124 /* Port C */
125 { /* conf ppar psor pdir podr pdat */
126 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
127 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
128 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
129 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
130 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
131 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
132 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
133 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
134 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
135 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
136 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
137 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
138 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
139 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
140 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
141 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
142 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
143 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
144 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
145 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
146 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
147 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
148 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
149 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
150 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
151 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
152 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
153 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
154 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
155 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
156 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
157 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
158 },
159
160 /* Port D */
161 { /* conf ppar psor pdir podr pdat */
162 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
163 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
164 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
165 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
166 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
167 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
168 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
169 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
170 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
171 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
172 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
173 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
174 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
175 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
176 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
177 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
178 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
179 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
180 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
181 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
182 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
183 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
184 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
185 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
186 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
187 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
188 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
189 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
190 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
194 }
195};
196
wdenk5c952cf2004-10-10 21:27:30 +0000197int board_early_init_f (void)
wdenk03f5c552004-10-10 21:21:55 +0000198{
wdenk5c952cf2004-10-10 21:27:30 +0000199 return 0;
wdenk03f5c552004-10-10 21:21:55 +0000200}
201
wdenk5c952cf2004-10-10 21:27:30 +0000202int checkboard (void)
wdenk03f5c552004-10-10 21:21:55 +0000203{
wdenk5c952cf2004-10-10 21:27:30 +0000204 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
205 volatile ccsr_gur_t *gur = &immap->im_gur;
wdenk03f5c552004-10-10 21:21:55 +0000206
wdenk5c952cf2004-10-10 21:27:30 +0000207 /* PCI slot in USER bits CSR[6:7] by convention. */
208 uint pci_slot = get_pci_slot ();
wdenk03f5c552004-10-10 21:21:55 +0000209
wdenk5c952cf2004-10-10 21:27:30 +0000210 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
211 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
212 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
213 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
wdenk03f5c552004-10-10 21:21:55 +0000214
wdenk5c952cf2004-10-10 21:27:30 +0000215 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
wdenk03f5c552004-10-10 21:21:55 +0000216
wdenk5c952cf2004-10-10 21:27:30 +0000217 uint cpu_board_rev = get_cpu_board_revision ();
wdenk03f5c552004-10-10 21:21:55 +0000218
wdenk5c952cf2004-10-10 21:27:30 +0000219 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
220 get_board_version (), pci_slot);
wdenk03f5c552004-10-10 21:21:55 +0000221
wdenk5c952cf2004-10-10 21:27:30 +0000222 printf ("CPU Board Revision %d.%d (0x%04x)\n",
223 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
224 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
wdenk03f5c552004-10-10 21:21:55 +0000225
wdenk5c952cf2004-10-10 21:27:30 +0000226 printf (" PCI1: %d bit, %s MHz, %s\n",
227 (pci1_32) ? 32 : 64,
228 (pci1_speed == 33000000) ? "33" :
229 (pci1_speed == 66000000) ? "66" : "unknown",
230 pci1_clk_sel ? "sync" : "async");
wdenk03f5c552004-10-10 21:21:55 +0000231
wdenk5c952cf2004-10-10 21:27:30 +0000232 if (pci_dual) {
233 printf (" PCI2: 32 bit, 66 MHz, %s\n",
234 pci2_clk_sel ? "sync" : "async");
235 } else {
236 printf (" PCI2: disabled\n");
237 }
wdenk03f5c552004-10-10 21:21:55 +0000238
wdenk5c952cf2004-10-10 21:27:30 +0000239 /*
240 * Initialize local bus.
241 */
242 local_bus_init ();
wdenk03f5c552004-10-10 21:21:55 +0000243
wdenk5c952cf2004-10-10 21:27:30 +0000244 return 0;
wdenk03f5c552004-10-10 21:21:55 +0000245}
246
wdenk03f5c552004-10-10 21:21:55 +0000247long int
248initdram(int board_type)
249{
250 long dram_size = 0;
251 volatile immap_t *immap = (immap_t *)CFG_IMMR;
252
253 puts("Initializing\n");
254
255#if defined(CONFIG_DDR_DLL)
256 {
257 /*
258 * Work around to stabilize DDR DLL MSYNC_IN.
259 * Errata DDR9 seems to have been fixed.
260 * This is now the workaround for Errata DDR11:
261 * Override DLL = 1, Course Adj = 1, Tap Select = 0
262 */
263
264 volatile ccsr_gur_t *gur= &immap->im_gur;
265
266 gur->ddrdllcr = 0x81000000;
267 asm("sync;isync;msync");
268 udelay(200);
269 }
270#endif
wdenk03f5c552004-10-10 21:21:55 +0000271 dram_size = spd_sdram();
272
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500273#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk03f5c552004-10-10 21:21:55 +0000274 /*
275 * Initialize and enable DDR ECC.
276 */
277 ddr_enable_ecc(dram_size);
278#endif
wdenk03f5c552004-10-10 21:21:55 +0000279 /*
280 * SDRAM Initialization
281 */
282 sdram_init();
283
284 puts(" DDR: ");
285 return dram_size;
286}
287
wdenk03f5c552004-10-10 21:21:55 +0000288/*
289 * Initialize Local Bus
290 */
wdenk03f5c552004-10-10 21:21:55 +0000291void
292local_bus_init(void)
293{
294 volatile immap_t *immap = (immap_t *)CFG_IMMR;
295 volatile ccsr_gur_t *gur = &immap->im_gur;
296 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
297
298 uint clkdiv;
299 uint lbc_hz;
300 sys_info_t sysinfo;
301 uint temp_lbcdll;
302
303 /*
304 * Errata LBC11.
305 * Fix Local Bus clock glitch when DLL is enabled.
306 *
307 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
308 * If localbus freq is > 133Mhz, DLL can be safely enabled.
309 * Between 66 and 133, the DLL is enabled with an override workaround.
310 */
311
312 get_sys_info(&sysinfo);
313 clkdiv = lbc->lcrr & 0x0f;
314 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
315
316 if (lbc_hz < 66) {
317 lbc->lcrr |= 0x80000000; /* DLL Bypass */
318
319 } else if (lbc_hz >= 133) {
320 lbc->lcrr &= (~0x80000000); /* DLL Enabled */
321
322 } else {
323 lbc->lcrr &= (~0x8000000); /* DLL Enabled */
324 udelay(200);
325
326 /*
327 * Sample LBC DLL ctrl reg, upshift it to set the
328 * override bits.
329 */
330 temp_lbcdll = gur->lbcdllcr;
331 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
332 asm("sync;isync;msync");
333 }
334}
335
wdenk03f5c552004-10-10 21:21:55 +0000336/*
337 * Initialize SDRAM memory on the Local Bus.
338 */
wdenk03f5c552004-10-10 21:21:55 +0000339void
340sdram_init(void)
341{
342#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
343
344 uint idx;
345 volatile immap_t *immap = (immap_t *)CFG_IMMR;
346 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
347 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
348 uint cpu_board_rev;
349 uint lsdmr_common;
350
351 puts(" SDRAM: ");
352
353 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
354
355 /*
356 * Setup SDRAM Base and Option Registers
357 */
358 lbc->or2 = CFG_OR2_PRELIM;
359 asm("msync");
360
361 lbc->br2 = CFG_BR2_PRELIM;
362 asm("msync");
363
364 lbc->lbcr = CFG_LBC_LBCR;
365 asm("msync");
366
wdenk03f5c552004-10-10 21:21:55 +0000367 lbc->lsrt = CFG_LBC_LSRT;
368 lbc->mrtpr = CFG_LBC_MRTPR;
369 asm("msync");
370
371 /*
372 * Determine which address lines to use baed on CPU board rev.
373 */
374 cpu_board_rev = get_cpu_board_revision();
375 lsdmr_common = CFG_LBC_LSDMR_COMMON;
376 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
377 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
378 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
379 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
380 } else {
381 /*
382 * Assume something unable to identify itself is
383 * really old, and likely has lines 16/17 mapped.
384 */
385 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
386 }
387
388 /*
389 * Issue PRECHARGE ALL command.
390 */
391 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
392 asm("sync;msync");
393 *sdram_addr = 0xff;
394 ppcDcbf((unsigned long) sdram_addr);
395 udelay(100);
396
397 /*
398 * Issue 8 AUTO REFRESH commands.
399 */
400 for (idx = 0; idx < 8; idx++) {
401 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
402 asm("sync;msync");
403 *sdram_addr = 0xff;
404 ppcDcbf((unsigned long) sdram_addr);
405 udelay(100);
406 }
407
408 /*
409 * Issue 8 MODE-set command.
410 */
411 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
412 asm("sync;msync");
413 *sdram_addr = 0xff;
414 ppcDcbf((unsigned long) sdram_addr);
415 udelay(100);
416
417 /*
418 * Issue NORMAL OP command.
419 */
420 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
421 asm("sync;msync");
422 *sdram_addr = 0xff;
423 ppcDcbf((unsigned long) sdram_addr);
424 udelay(200); /* Overkill. Must wait > 200 bus cycles */
425
426#endif /* enable SDRAM init */
427}
428
wdenk03f5c552004-10-10 21:21:55 +0000429#if defined(CFG_DRAM_TEST)
430int
431testdram(void)
432{
433 uint *pstart = (uint *) CFG_MEMTEST_START;
434 uint *pend = (uint *) CFG_MEMTEST_END;
435 uint *p;
436
437 printf("Testing DRAM from 0x%08x to 0x%08x\n",
438 CFG_MEMTEST_START,
439 CFG_MEMTEST_END);
440
441 printf("DRAM test phase 1:\n");
442 for (p = pstart; p < pend; p++)
443 *p = 0xaaaaaaaa;
444
445 for (p = pstart; p < pend; p++) {
446 if (*p != 0xaaaaaaaa) {
447 printf ("DRAM test fails at: %08x\n", (uint) p);
448 return 1;
449 }
450 }
451
452 printf("DRAM test phase 2:\n");
453 for (p = pstart; p < pend; p++)
454 *p = 0x55555555;
455
456 for (p = pstart; p < pend; p++) {
457 if (*p != 0x55555555) {
458 printf ("DRAM test fails at: %08x\n", (uint) p);
459 return 1;
460 }
461 }
462
463 printf("DRAM test passed.\n");
464 return 0;
465}
466#endif
467
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500468#ifdef CONFIG_PCI
469/* For some reason the Tundra PCI bridge shows up on itself as a
470 * different device. Work around that by refusing to configure it
wdenk03f5c552004-10-10 21:21:55 +0000471 */
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500472void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
wdenk03f5c552004-10-10 21:21:55 +0000473
wdenk03f5c552004-10-10 21:21:55 +0000474static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500475 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
476 {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600477 {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
478 mpc85xx_config_via_usbide, {0,0,0}},
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500479 {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
480 {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600481 {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
482 mpc85xx_config_via_power, {0,0,0}},
483 {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
484 {},
wdenk03f5c552004-10-10 21:21:55 +0000485};
wdenk03f5c552004-10-10 21:21:55 +0000486
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500487
488static struct pci_controller hose[] = {
489 {
wdenk03f5c552004-10-10 21:21:55 +0000490 config_table: pci_mpc85xxcds_config_table,
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500491 },
492#ifdef CONFIG_MPC85XX_PCI2
Andy Flemingffa621a2007-02-24 01:08:13 -0600493 {},
wdenk03f5c552004-10-10 21:21:55 +0000494#endif
495};
496
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500497#endif
wdenk03f5c552004-10-10 21:21:55 +0000498
wdenk03f5c552004-10-10 21:21:55 +0000499void
500pci_init_board(void)
501{
502#ifdef CONFIG_PCI
Matthew McClintocke4c2a0e2006-06-28 10:46:35 -0500503 pci_mpc85xx_init(hose);
wdenk03f5c552004-10-10 21:21:55 +0000504#endif
505}