blob: cc3891fd6dfd4bec0cf057d9aeb332483f1f6db8 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07002/**
3 * (C) Copyright 2014, Cavium Inc.
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07004**/
5
6#ifndef __THUNDERX_88XX_H__
7#define __THUNDERX_88XX_H__
8
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07009#define CONFIG_THUNDERX
10
11#define CONFIG_SYS_64BIT
12
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070013#define MEM_BASE 0x00500000
14
Sergey Temerkhanov900f88f2015-10-14 09:55:51 -070015#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
16
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070017/* Link Definitions */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070018
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070019/* SMP Spin Table Definitions */
20#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
21
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070022/* PL011 Serial Configuration */
23
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070024#define CONFIG_PL011_CLOCK 24000000
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070025
26/* Generic Interrupt Controller Definitions */
27#define GICD_BASE (0x801000000000)
28#define GICR_BASE (0x801000002000)
29#define CONFIG_SYS_SERIAL0 0x87e024000000
30#define CONFIG_SYS_SERIAL1 0x87e025000000
31
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070032/* Miscellaneous configurable options */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070033
34/* Physical Memory Map */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070035#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
36#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
37#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
38
39/* Initial environment variables */
40#define UBOOT_IMG_HEAD_SIZE 0x40
41/* C80000 - 0x40 */
42#define CONFIG_EXTRA_ENV_SETTINGS \
43 "kernel_addr=08007ffc0\0" \
44 "fdt_addr=0x94C00000\0" \
45 "fdt_high=0x9fffffff\0"
46
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070047/* Do not preserve environment */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070048
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070049#define PLL_REF_CLK 50000000 /* 50 MHz */
50#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
51
52#endif /* __THUNDERX_88XX_H__ */