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Vitaly Andrianovef509b92014-04-04 13:16:53 -04001/*
Hao Zhange5951072014-07-09 23:44:46 +03002 * Keystone : Board initialization
Vitaly Andrianovef509b92014-04-04 13:16:53 -04003 *
Hao Zhange5951072014-07-09 23:44:46 +03004 * (C) Copyright 2014
Vitaly Andrianovef509b92014-04-04 13:16:53 -04005 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
Vitaly Andrianovb8dafa22016-03-11 08:23:04 -050011#include "board.h"
Hao Zhang5ec66b12014-10-22 16:32:31 +030012#include <spl.h>
Vitaly Andrianovef509b92014-04-04 13:16:53 -040013#include <exports.h>
14#include <fdt_support.h>
Khoronzhuk, Ivan0b868582014-07-09 19:48:40 +030015#include <asm/arch/ddr3.h>
Khoronzhuk, Ivan497e9e02014-09-29 22:17:24 +030016#include <asm/arch/psc_defs.h>
Lokesh Vutla8626cb82015-10-08 11:31:47 +053017#include <asm/arch/clock.h>
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030018#include <asm/ti-common/ti-aemif.h>
Khoronzhuk, Ivan0935cac2014-09-29 22:17:22 +030019#include <asm/ti-common/keystone_net.h>
Vitaly Andrianovef509b92014-04-04 13:16:53 -040020
21DECLARE_GLOBAL_DATA_PTR;
22
Lokesh Vutla8f695232016-04-13 09:50:59 +053023#if defined(CONFIG_TI_AEMIF)
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030024static struct aemif_config aemif_configs[] = {
Vitaly Andrianovef509b92014-04-04 13:16:53 -040025 { /* CS0 */
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030026 .mode = AEMIF_MODE_NAND,
Vitaly Andrianovef509b92014-04-04 13:16:53 -040027 .wr_setup = 0xf,
28 .wr_strobe = 0x3f,
29 .wr_hold = 7,
30 .rd_setup = 0xf,
31 .rd_strobe = 0x3f,
32 .rd_hold = 7,
33 .turn_around = 3,
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030034 .width = AEMIF_WIDTH_8,
Vitaly Andrianovef509b92014-04-04 13:16:53 -040035 },
Vitaly Andrianovef509b92014-04-04 13:16:53 -040036};
Lokesh Vutla8f695232016-04-13 09:50:59 +053037#endif
Vitaly Andrianovef509b92014-04-04 13:16:53 -040038
39int dram_init(void)
40{
Vitaly Andrianov66c98a02015-02-11 14:07:58 -050041 u32 ddr3_size;
42
43 ddr3_size = ddr3_init();
Vitaly Andrianovef509b92014-04-04 13:16:53 -040044
45 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
46 CONFIG_MAX_RAM_BANK_SIZE);
Lokesh Vutla8f695232016-04-13 09:50:59 +053047#if defined(CONFIG_TI_AEMIF)
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030048 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
Lokesh Vutla8f695232016-04-13 09:50:59 +053049#endif
50
Vitaly Andrianov235dd6e2015-09-19 16:26:43 +053051 if (ddr3_size)
52 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040053 return 0;
54}
55
Hao Zhange5951072014-07-09 23:44:46 +030056int board_init(void)
57{
Nishanth Menon59d4cd22015-07-22 18:05:43 -050058 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040059
Hao Zhange5951072014-07-09 23:44:46 +030060 return 0;
61}
62
63#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
Mugunthan V N03690082016-02-02 15:51:31 +053064#ifndef CONFIG_DM_ETH
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040065int get_eth_env_param(char *env_name)
66{
67 char *env;
Hao Zhange5951072014-07-09 23:44:46 +030068 int res = -1;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040069
70 env = getenv(env_name);
71 if (env)
72 res = simple_strtol(env, NULL, 0);
73
74 return res;
75}
76
77int board_eth_init(bd_t *bis)
78{
Hao Zhange5951072014-07-09 23:44:46 +030079 int j;
80 int res;
81 int port_num;
82 char link_type_name[32];
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040083
Vitaly Andrianov91266cc2015-09-19 16:26:52 +053084 if (cpu_is_k2g())
85 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
86
Khoronzhuk, Ivan497e9e02014-09-29 22:17:24 +030087 /* By default, select PA PLL clock as PA clock source */
Vitaly Andrianov91266cc2015-09-19 16:26:52 +053088#ifndef CONFIG_SOC_K2G
Khoronzhuk, Ivan497e9e02014-09-29 22:17:24 +030089 if (psc_enable_module(KS2_LPSC_PA))
90 return -1;
Vitaly Andrianov91266cc2015-09-19 16:26:52 +053091#endif
Khoronzhuk, Ivan497e9e02014-09-29 22:17:24 +030092 if (psc_enable_module(KS2_LPSC_CPGMAC))
93 return -1;
94 if (psc_enable_module(KS2_LPSC_CRYPTO))
95 return -1;
96
Lokesh Vutla8626cb82015-10-08 11:31:47 +053097 if (cpu_is_k2e() || cpu_is_k2l())
98 pll_pa_clk_sel();
99
Hao Zhange5951072014-07-09 23:44:46 +0300100 port_num = get_num_eth_ports();
101
102 for (j = 0; j < port_num; j++) {
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400103 sprintf(link_type_name, "sgmii%d_link_type", j);
104 res = get_eth_env_param(link_type_name);
105 if (res >= 0)
106 eth_priv_cfg[j].sgmii_link_type = res;
107
108 keystone2_emac_initialize(&eth_priv_cfg[j]);
109 }
110
111 return 0;
112}
113#endif
Mugunthan V N03690082016-02-02 15:51:31 +0530114#endif
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400115
Hao Zhang5ec66b12014-10-22 16:32:31 +0300116#ifdef CONFIG_SPL_BUILD
117void spl_board_init(void)
118{
119 spl_init_keystone_plls();
120 preloader_console_init();
121}
122
123u32 spl_boot_device(void)
124{
125#if defined(CONFIG_SPL_SPI_LOAD)
126 return BOOT_DEVICE_SPI;
127#else
128 puts("Unknown boot device\n");
129 hang();
130#endif
131}
132#endif
133
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400134#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600135int ft_board_setup(void *blob, bd_t *bd)
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400136{
Hao Zhange5951072014-07-09 23:44:46 +0300137 int lpae;
138 char *env;
139 char *endp;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400140 int nbanks;
Hao Zhange5951072014-07-09 23:44:46 +0300141 u64 size[2];
142 u64 start[2];
Hao Zhange5951072014-07-09 23:44:46 +0300143 int nodeoffset;
144 u32 ddr3a_size;
145 int unitrd_fixup = 0;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400146
147 env = getenv("mem_lpae");
148 lpae = env && simple_strtol(env, NULL, 0);
Murali Karicheri0bedbb82014-07-09 23:44:45 +0300149 env = getenv("uinitrd_fixup");
150 unitrd_fixup = env && simple_strtol(env, NULL, 0);
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400151
152 ddr3a_size = 0;
153 if (lpae) {
Vitaly Andrianov8efc2432016-03-04 10:36:43 -0600154 ddr3a_size = ddr3_get_size();
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400155 if ((ddr3a_size != 8) && (ddr3a_size != 4))
156 ddr3a_size = 0;
157 }
158
159 nbanks = 1;
160 start[0] = bd->bi_dram[0].start;
161 size[0] = bd->bi_dram[0].size;
162
163 /* adjust memory start address for LPAE */
164 if (lpae) {
Hao Zhange5951072014-07-09 23:44:46 +0300165 start[0] -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400166 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
167 }
168
169 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
170 size[1] = ((u64)ddr3a_size - 2) << 30;
171 start[1] = 0x880000000;
172 nbanks++;
173 }
174
175 /* reserve memory at start of bank */
Khoronzhuk, Ivan30491fc2014-11-04 20:48:47 +0200176 env = getenv("mem_reserve_head");
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400177 if (env) {
178 start[0] += ustrtoul(env, &endp, 0);
179 size[0] -= ustrtoul(env, &endp, 0);
180 }
181
Khoronzhuk, Ivan30491fc2014-11-04 20:48:47 +0200182 env = getenv("mem_reserve");
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400183 if (env)
184 size[0] -= ustrtoul(env, &endp, 0);
185
186 fdt_fixup_memory_banks(blob, start, size, nbanks);
187
188 /* Fix up the initrd */
Murali Karicheri0bedbb82014-07-09 23:44:45 +0300189 if (lpae && unitrd_fixup) {
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400190 int err;
Hao Zhange5951072014-07-09 23:44:46 +0300191 u32 *prop1, *prop2;
192 u64 initrd_start, initrd_end;
Murali Karicheri0bedbb82014-07-09 23:44:45 +0300193
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400194 nodeoffset = fdt_path_offset(blob, "/chosen");
195 if (nodeoffset >= 0) {
196 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
197 "linux,initrd-start", NULL);
198 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
199 "linux,initrd-end", NULL);
200 if (prop1 && prop2) {
201 initrd_start = __be32_to_cpu(*prop1);
Hao Zhange5951072014-07-09 23:44:46 +0300202 initrd_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400203 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
204 initrd_start = __cpu_to_be64(initrd_start);
205 initrd_end = __be32_to_cpu(*prop2);
Hao Zhange5951072014-07-09 23:44:46 +0300206 initrd_end -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400207 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
208 initrd_end = __cpu_to_be64(initrd_end);
209
210 err = fdt_delprop(blob, nodeoffset,
211 "linux,initrd-start");
212 if (err < 0)
213 puts("error deleting initrd-start\n");
214
215 err = fdt_delprop(blob, nodeoffset,
216 "linux,initrd-end");
217 if (err < 0)
218 puts("error deleting initrd-end\n");
219
220 err = fdt_setprop(blob, nodeoffset,
221 "linux,initrd-start",
222 &initrd_start,
223 sizeof(initrd_start));
224 if (err < 0)
225 puts("error adding initrd-start\n");
226
227 err = fdt_setprop(blob, nodeoffset,
228 "linux,initrd-end",
229 &initrd_end,
230 sizeof(initrd_end));
231 if (err < 0)
232 puts("error adding linux,initrd-end\n");
233 }
234 }
235 }
Simon Glasse895a4b2014-10-23 18:58:47 -0600236
237 return 0;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400238}
239
240void ft_board_setup_ex(void *blob, bd_t *bd)
241{
Hao Zhange5951072014-07-09 23:44:46 +0300242 int lpae;
243 u64 size;
244 char *env;
245 u64 *reserve_start;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400246
247 env = getenv("mem_lpae");
248 lpae = env && simple_strtol(env, NULL, 0);
249
250 if (lpae) {
251 /*
252 * the initrd and other reserved memory areas are
253 * embedded in in the DTB itslef. fix up these addresses
254 * to 36 bit format
255 */
256 reserve_start = (u64 *)((char *)blob +
257 fdt_off_mem_rsvmap(blob));
258 while (1) {
259 *reserve_start = __cpu_to_be64(*reserve_start);
260 size = __cpu_to_be64(*(reserve_start + 1));
261 if (size) {
Hao Zhange5951072014-07-09 23:44:46 +0300262 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400263 *reserve_start +=
264 CONFIG_SYS_LPAE_SDRAM_BASE;
265 *reserve_start =
266 __cpu_to_be64(*reserve_start);
267 } else {
268 break;
269 }
270 reserve_start += 2;
271 }
272 }
Vitaly Andrianov89f44bb2014-10-22 17:47:58 +0300273
274 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400275}
276#endif