Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Masahiro Yamada | b08c8c4 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 8 | #include <linux/libfdt.h> |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 9 | #include <linux/err.h> |
| 10 | #include <asm/arch/gxbb.h> |
Beniamino Galvani | c7757d4 | 2016-05-08 08:30:17 +0200 | [diff] [blame] | 11 | #include <asm/arch/sm.h> |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 12 | #include <asm/armv8/mmu.h> |
| 13 | #include <asm/unaligned.h> |
Neil Armstrong | c7be3e5 | 2017-11-27 10:35:46 +0100 | [diff] [blame] | 14 | #include <linux/sizes.h> |
| 15 | #include <efi_loader.h> |
| 16 | #include <asm/io.h> |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
| 20 | int dram_init(void) |
| 21 | { |
| 22 | const fdt64_t *val; |
| 23 | int offset; |
| 24 | int len; |
| 25 | |
| 26 | offset = fdt_path_offset(gd->fdt_blob, "/memory"); |
| 27 | if (offset < 0) |
| 28 | return -EINVAL; |
| 29 | |
| 30 | val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); |
| 31 | if (len < sizeof(*val) * 2) |
| 32 | return -EINVAL; |
| 33 | |
| 34 | /* Use unaligned access since cache is still disabled */ |
| 35 | gd->ram_size = get_unaligned_be64(&val[1]); |
| 36 | |
| 37 | return 0; |
| 38 | } |
| 39 | |
Neil Armstrong | c7be3e5 | 2017-11-27 10:35:46 +0100 | [diff] [blame] | 40 | phys_size_t get_effective_memsize(void) |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 41 | { |
Neil Armstrong | c7be3e5 | 2017-11-27 10:35:46 +0100 | [diff] [blame] | 42 | /* Size is reported in MiB, convert it in bytes */ |
| 43 | return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK) |
| 44 | >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M; |
| 45 | } |
| 46 | |
| 47 | static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size) |
| 48 | { |
| 49 | int ret; |
| 50 | |
| 51 | ret = fdt_add_mem_rsv(fdt, start, size); |
| 52 | if (ret) |
| 53 | printf("Could not reserve zone @ 0x%llx\n", start); |
| 54 | |
| 55 | if (IS_ENABLED(CONFIG_EFI_LOADER)) { |
| 56 | efi_add_memory_map(start, |
| 57 | ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, |
| 58 | EFI_RESERVED_MEMORY_TYPE, false); |
| 59 | } |
| 60 | } |
| 61 | |
| 62 | void meson_gx_init_reserved_memory(void *fdt) |
| 63 | { |
| 64 | u64 bl31_size, bl31_start; |
| 65 | u64 bl32_size, bl32_start; |
| 66 | u32 reg; |
| 67 | |
| 68 | /* |
| 69 | * Get ARM Trusted Firmware reserved memory zones in : |
| 70 | * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 |
| 71 | * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL |
| 72 | * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL |
| 73 | */ |
| 74 | |
| 75 | reg = readl(GXBB_AO_SEC_GP_CFG3); |
| 76 | |
| 77 | bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK) |
| 78 | >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; |
| 79 | bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; |
| 80 | |
| 81 | bl31_start = readl(GXBB_AO_SEC_GP_CFG5); |
| 82 | bl32_start = readl(GXBB_AO_SEC_GP_CFG4); |
| 83 | |
| 84 | /* |
| 85 | * Early Meson GXBB Firmware revisions did not provide the reserved |
| 86 | * memory zones in the registers, keep fixed memory zone handling. |
| 87 | */ |
| 88 | if (IS_ENABLED(CONFIG_MESON_GXBB) && |
| 89 | !reg && !bl31_start && !bl32_start) { |
| 90 | bl31_start = 0x10000000; |
| 91 | bl31_size = 0x200000; |
| 92 | } |
| 93 | |
| 94 | /* Add first 16MiB reserved zone */ |
| 95 | meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE); |
| 96 | |
| 97 | /* Add BL31 reserved zone */ |
| 98 | if (bl31_start && bl31_size) |
| 99 | meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); |
| 100 | |
| 101 | /* Add BL32 reserved zone */ |
| 102 | if (bl32_start && bl32_size) |
| 103 | meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | void reset_cpu(ulong addr) |
| 107 | { |
Alexander Graf | 51bfb5b | 2016-08-16 21:08:46 +0200 | [diff] [blame] | 108 | psci_system_reset(); |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | static struct mm_region gxbb_mem_map[] = { |
| 112 | { |
York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 113 | .virt = 0x0UL, |
| 114 | .phys = 0x0UL, |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 115 | .size = 0x80000000UL, |
| 116 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 117 | PTE_BLOCK_INNER_SHARE |
| 118 | }, { |
York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 119 | .virt = 0x80000000UL, |
| 120 | .phys = 0x80000000UL, |
Beniamino Galvani | bfcef28 | 2016-05-08 08:30:16 +0200 | [diff] [blame] | 121 | .size = 0x80000000UL, |
| 122 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 123 | PTE_BLOCK_NON_SHARE | |
| 124 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 125 | }, { |
| 126 | /* List terminator */ |
| 127 | 0, |
| 128 | } |
| 129 | }; |
| 130 | |
| 131 | struct mm_region *mem_map = gxbb_mem_map; |