blob: 736d65caa16b63df32ef80295881164d6263c1e8 [file] [log] [blame]
Albert Aribaudce9c2272010-06-17 19:38:21 +05301/*
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +02002 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaudce9c2272010-06-17 19:38:21 +05303 *
4 * (C) Copyright 2009
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Albert Aribaudce9c2272010-06-17 19:38:21 +05309 */
10
11#include <common.h>
12#include <miiphy.h>
13#include <asm/arch/orion5x.h>
Wolfgang Denk85e04b72011-12-09 12:14:28 +010014#include "../common/common.h"
Albert ARIBAUD9608e7d2015-01-31 22:55:38 +010015#include <spl.h>
16#include <ns16550.h>
Simon Glassc62db352017-05-31 19:47:48 -060017#include <asm/mach-types.h>
Albert Aribaudce9c2272010-06-17 19:38:21 +053018
19DECLARE_GLOBAL_DATA_PTR;
20
Albert Aribaudce9c2272010-06-17 19:38:21 +053021int board_init(void)
22{
23 /* arch number of board */
24 gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
25
26 /* boot parameter start at 256th byte of RAM base */
27 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
28
29 return 0;
30}
Albert Aribaudab9164d2010-07-12 22:24:30 +020031
32#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
33/* Configure and enable MV88E1116 PHY */
34void reset_phy(void)
35{
Simon Guinotc59c0852012-06-05 13:16:00 +000036 mv_phy_88e1116_init("egiga0", 8);
Albert Aribaudab9164d2010-07-12 22:24:30 +020037}
38#endif /* CONFIG_RESET_PHY_R */
Albert ARIBAUD9608e7d2015-01-31 22:55:38 +010039
40/*
41 * SPL serial setup and NOR boot device selection
42 */
43
44#ifdef CONFIG_SPL_BUILD
45
46void spl_board_init(void)
47{
48 preloader_console_init();
49}
50
51u32 spl_boot_device(void)
52{
53 return BOOT_DEVICE_NOR;
54}
55
56#endif /* CONFIG_SPL_BUILD */