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Wills Wang6a7b52b2016-03-16 16:59:59 +08001/*
2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/addrspace.h>
10#include <asm/types.h>
11#include <mach/ar71xx_regs.h>
12#include <mach/ddr.h>
Wills Wang04583c62016-05-30 22:54:51 +080013#include <mach/ath79.h>
Wills Wang6a7b52b2016-03-16 16:59:59 +080014#include <debug_uart.h>
15
Wills Wang6a7b52b2016-03-16 16:59:59 +080016#ifdef CONFIG_DEBUG_UART_BOARD_INIT
17void board_debug_uart_init(void)
18{
19 void __iomem *regs;
20 u32 val;
21
22 regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
23 MAP_NOCACHE);
24
25 /*
26 * GPIO9 as input, GPIO10 as output
27 */
28 val = readl(regs + AR71XX_GPIO_REG_OE);
29 val &= ~AR933X_GPIO(9);
30 val |= AR933X_GPIO(10);
31 writel(val, regs + AR71XX_GPIO_REG_OE);
32
33 /*
34 * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
35 */
36 val = readl(regs + AR71XX_GPIO_REG_FUNC);
37 val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
38 writel(val, regs + AR71XX_GPIO_REG_FUNC);
39}
40#endif
41
42int board_early_init_f(void)
43{
Wills Wang6a7b52b2016-03-16 16:59:59 +080044 ddr_init();
Wills Wang04583c62016-05-30 22:54:51 +080045 ath79_eth_reset();
Wills Wang6a7b52b2016-03-16 16:59:59 +080046 return 0;
47}