blob: 159120edd6c621d77caedf89032bb269ffa1efc5 [file] [log] [blame]
Boris BREZILLON058d2312015-03-04 13:13:05 +01001/*
2 * Copyright (C) 2013 Seco USA Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 *
6 * Refer doc/README.imximage for more details about how-to configure
7 * and create imximage boot image
8 *
9 * The syntax is taken as close as possible with the kwbimage
10 */
11
12/* image version */
13IMAGE_VERSION 2
14
15/*
16 * Boot Device : one of
17 * spi, sd (the board has no nand neither onenand)
18 */
19BOOT_FROM sd
20
21#define __ASSEMBLY__
22#include <config.h>
23#include "asm/arch/mx6-ddr.h"
24#include "asm/arch/iomux.h"
25#include "asm/arch/crm_regs.h"
26
27/* DDR IO TYPE */
28DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
29DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
30
31/* DATA STROBE */
32DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
33DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
34DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
35DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
36DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
37DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
38DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
39DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
40DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
41
42/* DATA */
43DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
44DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
45DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
46DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
47DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
48DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
49DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
50DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
51DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
52DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
53DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
54DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
55DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
56DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
57DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
58DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
59DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
60/* ADDRESS */
61DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028
62DATA 4, MX6_IOM_DRAM_CAS, 0x00000028
63DATA 4, MX6_IOM_DRAM_RAS, 0x00000028
64
65/* CONTROL */
66DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
67DATA 4, MX6_IOM_DRAM_RESET, 0x00000028
68DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
69DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028
70DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028
71
72/* CLOCK */
73DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
74DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
75
76/*
77 * DDR3 SETTINGS
78 * Read Data Bit Delay
79 */
80DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
81DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
82DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
83DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
84DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
85DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
86DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
87DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
88
89
90/* Write Leveling */
91DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
92DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
93DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001
94DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
95
96/* DQS gating, read delay, write delay calibration values */
97DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326
98DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B
99DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340
100DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C
101
102/* Read calibration */
103DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137
104DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45
105
106/* write calibration */
107DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741
108DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C
109
110/* Complete calibration by forced measurement: */
111DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
112DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
113
114/*
115 * MMDC init:
116 * in DDR3, 64-bit mode, only MMDC0 is init
117 */
118DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
119DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
120
121DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955
122DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
123DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
124
125DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
126DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
127DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
128DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
129
130/* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
131DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
132
133/* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
134DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
135
136/* Initialize DDR3 on CS_0 and CS_1 */
137DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032
138DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
139DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
140
141/* P0 01c */
142/* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
143DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
144
145/*ZQ - Calibrationi */
146DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
147DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
148DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
149
150DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
151DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
152
153DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
154
155DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
156DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
157
158/* set the default clock gate to save power */
159DATA 4, CCM_CCGR0, 0x00C03F3F
160DATA 4, CCM_CCGR1, 0x0030FC03
161DATA 4, CCM_CCGR2, 0x0FFFC000
162DATA 4, CCM_CCGR3, 0x3FF00000
163DATA 4, CCM_CCGR4, 0x00FFF300
164DATA 4, CCM_CCGR5, 0x0F0000C3
165DATA 4, CCM_CCGR6, 0x000003FF
166
167/* enable AXI cache for VDOA/VPU/IPU */
168DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
169
170/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
171DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
172DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
173