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Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +09001/*
2 * Configuation settings for the Hitachi Solution Engine 7720
3 *
4 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +09007 */
8
9#ifndef __MS7720SE_H
10#define __MS7720SE_H
11
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090012#define CONFIG_CPU_SH7720 1
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090013
Joe Hershbergerb3f44c22011-10-13 13:03:48 +000014#define CONFIG_BOOTFILE "/boot/zImage"
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090015#define CONFIG_LOADADDR 0x8E000000
16
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020017#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090018#undef CONFIG_SHOW_BOOT_PROGRESS
19
20/* MEMORY */
21#define MS7720SE_SDRAM_BASE 0x8C000000
22#define MS7720SE_FLASH_BASE_1 0xA0000000
23#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
24
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090026/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090028
29/* SCIF */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090030#define CONFIG_CONS_SCIF0 1
31
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
33#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090034
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
36#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090037
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
39#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
40#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
41#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090043
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090044/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020046#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#undef CONFIG_SYS_FLASH_QUIET_TEST
48#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090049
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MAX_FLASH_SECT 150
53#define CONFIG_SYS_MAX_FLASH_BANKS 1
54#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090055
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020056#define CONFIG_ENV_SECT_SIZE (64 * 1024)
57#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
59#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
60#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090061
62/* Board Clock */
63#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090064#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
65#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020066#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090067
68/* PCMCIA */
69#define CONFIG_IDE_PCMCIA 1
70#define CONFIG_MARUBUN_PCCARD 1
71#define CONFIG_PCMCIA_SLOT_A 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_IDE_MAXDEVICE 1
73#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
74#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
75#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
76#define CONFIG_SYS_MARUBUN_IO 0xb8600000
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_PIO_MODE 1
79#define CONFIG_SYS_IDE_MAXBUS 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
81#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
82#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
83#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
84#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +053085#define CONFIG_IDE_SWAP_IO
Yoshihiro Shimodab2b5e2b2007-12-03 22:58:50 +090086
87#endif /* __MS7720SE_H */