Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Configuation settings for the Hitachi Solution Engine 7720 |
| 3 | * |
| 4 | * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __MS7720SE_H |
| 10 | #define __MS7720SE_H |
| 11 | |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 12 | #define CONFIG_CPU_SH7720 1 |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 13 | |
Joe Hershberger | b3f44c2 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 14 | #define CONFIG_BOOTFILE "/boot/zImage" |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 15 | #define CONFIG_LOADADDR 0x8E000000 |
| 16 | |
Vladimir Zapolskiy | 18a40e8 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 17 | #define CONFIG_DISPLAY_BOARDINFO |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 18 | #undef CONFIG_SHOW_BOOT_PROGRESS |
| 19 | |
| 20 | /* MEMORY */ |
| 21 | #define MS7720SE_SDRAM_BASE 0x8C000000 |
| 22 | #define MS7720SE_FLASH_BASE_1 0xA0000000 |
| 23 | #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) |
| 24 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 25 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 26 | /* List of legal baudrate settings for this board */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 27 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 28 | |
| 29 | /* SCIF */ |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 30 | #define CONFIG_CONS_SCIF0 1 |
| 31 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | #define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE |
| 33 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 34 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 35 | #define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE |
| 36 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 37 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 38 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
| 39 | #define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1 |
| 40 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
| 41 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 42 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 43 | |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 44 | /* FLASH */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 45 | #define CONFIG_SYS_FLASH_CFI |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 46 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
| 48 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 49 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 50 | #define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1 |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 51 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_MAX_FLASH_SECT 150 |
| 53 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 54 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 55 | |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 56 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) |
| 57 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 58 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 59 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
| 60 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 61 | |
| 62 | /* Board Clock */ |
| 63 | #define CONFIG_SYS_CLK_FREQ 33333333 |
Nobuhiro Iwamatsu | 684a501 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 64 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
| 65 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Jean-Christophe PLAGNIOL-VILLARD | be45c63 | 2009-06-04 12:06:48 +0200 | [diff] [blame] | 66 | #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 67 | |
| 68 | /* PCMCIA */ |
| 69 | #define CONFIG_IDE_PCMCIA 1 |
| 70 | #define CONFIG_MARUBUN_PCCARD 1 |
| 71 | #define CONFIG_PCMCIA_SLOT_A 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #define CONFIG_SYS_IDE_MAXDEVICE 1 |
| 73 | #define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0 |
| 74 | #define CONFIG_SYS_MARUBUN_MW1 0xb8400000 |
| 75 | #define CONFIG_SYS_MARUBUN_MW2 0xb8500000 |
| 76 | #define CONFIG_SYS_MARUBUN_IO 0xb8600000 |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 77 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | #define CONFIG_SYS_PIO_MODE 1 |
| 79 | #define CONFIG_SYS_IDE_MAXBUS 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 80 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */ |
| 81 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ |
| 82 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ |
| 83 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ |
| 84 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ |
Albert Aribaud | f2a37fc | 2010-08-08 05:17:05 +0530 | [diff] [blame] | 85 | #define CONFIG_IDE_SWAP_IO |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 86 | |
| 87 | #endif /* __MS7720SE_H */ |