Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 1 | /* |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 2 | * Copyright (C) 2014 Marek Vasut <marex@denx.de> |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 5 | */ |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 6 | #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ |
7 | #define __CONFIG_SOCFPGA_CYCLONE5_H__ | ||||
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 8 | |
Dinh Nguyen | 871c24b | 2015-11-23 17:27:17 -0600 | [diff] [blame] | 9 | #include <asm/arch/base_addr_ac5.h> |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 10 | |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 11 | /* Memory configurations */ |
Marek Vasut | 47f9b4e | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 12 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 13 | |
Marek Vasut | 47f9b4e | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 14 | /* Booting Linux */ |
Marek Vasut | 4c6d8b9 | 2015-07-22 06:18:19 +0200 | [diff] [blame] | 15 | #define CONFIG_LOADADDR 0x01000000 |
Marek Vasut | 47f9b4e | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 16 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
17 | |||||
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 18 | /* Ethernet on SoC (EMAC) */ |
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 19 | |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 20 | /* The rest of the configuration is shared */ |
21 | #include <configs/socfpga_common.h> | ||||
Dinh Nguyen | 7775440 | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 22 | |
Pavel Machek | 5095ee0 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 23 | #endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ |