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Patrice Chotardc0cdd5a2017-12-12 09:49:44 +01001/*
2 * Copyright (C) STMicroelectronics SA 2017
3 * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010011#define CONFIG_MISC_INIT_R
12
13#define CONFIG_SYS_FLASH_BASE 0x08000000
14
15#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010016
17#define CONFIG_SYS_ICACHE_OFF
18#define CONFIG_SYS_DCACHE_OFF
19
20/*
21 * Configuration of the external SDRAM memory
22 */
23#define CONFIG_NR_DRAM_BANKS 1
24#define CONFIG_SYS_RAM_FREQ_DIV 2
25#define CONFIG_SYS_RAM_BASE 0x00000000
26#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
27#define CONFIG_SYS_LOAD_ADDR 0x00400000
28#define CONFIG_LOADADDR 0x00400000
29
30#define CONFIG_SYS_MAX_FLASH_SECT 12
31#define CONFIG_SYS_MAX_FLASH_BANKS 2
32
33#define CONFIG_ENV_OFFSET (256 << 10)
34#define CONFIG_ENV_SECT_SIZE (128 << 10)
35#define CONFIG_ENV_SIZE (8 << 10)
36
37#define CONFIG_STM32_FLASH
38
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010039#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
40#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
41
42#define CONFIG_CMDLINE_TAG
43#define CONFIG_SETUP_MEMORY_TAGS
44#define CONFIG_INITRD_TAG
45#define CONFIG_REVISION_TAG
46
47#define CONFIG_SYS_CBSIZE 1024
48
49#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
50
51#define CONFIG_BOOTCOMMAND \
52 "run boot_sd"
53
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010054#define CONFIG_EXTRA_ENV_SETTINGS \
55 "boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32f469-disco.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
56
57/*
58 * Command line configuration.
59 */
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +010060
61#endif /* __CONFIG_H */