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stroesed4629c82003-05-23 11:30:39 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
stroesed4629c82003-05-23 11:30:39 +000038#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
40#define CONFIG_CPCI405AB 1 /* ...and special AB version */
stroesed4629c82003-05-23 11:30:39 +000041
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
43
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050045#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroesed4629c82003-05-23 11:30:39 +000046
stroesea20b27a2004-12-16 18:05:42 +000047#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
stroesed4629c82003-05-23 11:30:39 +000048
49#define CONFIG_BAUDRATE 9600
50#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
51
stroesed4629c82003-05-23 11:30:39 +000052#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000053#undef CONFIG_BOOTCOMMAND
54
55#define CONFIG_PREBOOT /* enable preboot variable */
stroesed4629c82003-05-23 11:30:39 +000056
wdenkc837dcb2004-01-20 23:12:12 +000057#undef CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesed4629c82003-05-23 11:30:39 +000059
Ben Warren96e21f82008-10-27 23:50:15 -070060#define CONFIG_PPC4xx_EMAC
stroesed4629c82003-05-23 11:30:39 +000061#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000062#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000063#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020064#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
65
Matthias Fuchs6f35c532007-06-24 17:41:21 +020066#undef CONFIG_HAS_ETH1
stroesed4629c82003-05-23 11:30:39 +000067
68#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
69
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050070/*
71 * BOOTP options
72 */
73#define CONFIG_BOOTP_SUBNETMASK
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76#define CONFIG_BOOTP_BOOTPATH
77#define CONFIG_BOOTP_DNS
78#define CONFIG_BOOTP_DNS2
79#define CONFIG_BOOTP_SEND_HOSTNAME
stroesed4629c82003-05-23 11:30:39 +000080
stroesed4629c82003-05-23 11:30:39 +000081
Jon Loeliger49cf7e82007-07-05 19:52:35 -050082/*
83 * Command line configuration.
84 */
85#include <config_cmd_default.h>
86
87#define CONFIG_CMD_DHCP
88#define CONFIG_CMD_PCI
89#define CONFIG_CMD_IRQ
90#define CONFIG_CMD_IDE
91#define CONFIG_CMD_FAT
92#define CONFIG_CMD_ELF
93#define CONFIG_CMD_DATE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050094#define CONFIG_CMD_I2C
95#define CONFIG_CMD_MII
96#define CONFIG_CMD_PING
Matthias Fuchs3ba605d2009-01-02 12:18:49 +010097#define CONFIG_CMD_BSP
Jon Loeliger49cf7e82007-07-05 19:52:35 -050098#define CONFIG_CMD_EEPROM
99
stroesed4629c82003-05-23 11:30:39 +0000100
101#define CONFIG_MAC_PARTITION
102#define CONFIG_DOS_PARTITION
103
stroesea20b27a2004-12-16 18:05:42 +0000104#define CONFIG_SUPPORT_VFAT
105
wdenkc837dcb2004-01-20 23:12:12 +0000106#undef CONFIG_WATCHDOG /* watchdog disabled */
stroesed4629c82003-05-23 11:30:39 +0000107
wdenkc837dcb2004-01-20 23:12:12 +0000108#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroesed4629c82003-05-23 11:30:39 +0000109
110/*
111 * Miscellaneous configurable options
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LONGHELP /* undef to save memory */
114#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroesed4629c82003-05-23 11:30:39 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
stroesed4629c82003-05-23 11:30:39 +0000117
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500118#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesed4629c82003-05-23 11:30:39 +0000120#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesed4629c82003-05-23 11:30:39 +0000122#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesed4629c82003-05-23 11:30:39 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesed4629c82003-05-23 11:30:39 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesed4629c82003-05-23 11:30:39 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
132#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesed4629c82003-05-23 11:30:39 +0000133
Stefan Roese550650d2010-09-20 16:05:31 +0200134#define CONFIG_CONS_INDEX 1 /* Use UART0 */
135#define CONFIG_SYS_NS16550
136#define CONFIG_SYS_NS16550_SERIAL
137#define CONFIG_SYS_NS16550_REG_SIZE 1
138#define CONFIG_SYS_NS16550_CLK get_serial_clock()
139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BASE_BAUD 691200
stroesed4629c82003-05-23 11:30:39 +0000142
143/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000145 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
146 57600, 115200, 230400, 460800, 921600 }
stroesed4629c82003-05-23 11:30:39 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
149#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesed4629c82003-05-23 11:30:39 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesed4629c82003-05-23 11:30:39 +0000152
Matthias Fuchsac53ee82008-09-05 15:34:04 +0200153#define CONFIG_CMDLINE_EDITING /* add command line history */
154
stroesed4629c82003-05-23 11:30:39 +0000155#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
156
wdenkc837dcb2004-01-20 23:12:12 +0000157#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroesed4629c82003-05-23 11:30:39 +0000158
Matthias Fuchs75511b42009-02-20 10:19:14 +0100159#define CONFIG_AUTOBOOT_KEYED 1
160#define CONFIG_AUTOBOOT_PROMPT \
161 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
162#undef CONFIG_AUTOBOOT_DELAY_STR
163#define CONFIG_AUTOBOOT_STOP_STR " "
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese53cf9432003-06-05 15:39:44 +0000166
stroesed4629c82003-05-23 11:30:39 +0000167/*-----------------------------------------------------------------------
168 * PCI stuff
169 *-----------------------------------------------------------------------
170 */
wdenkc837dcb2004-01-20 23:12:12 +0000171#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
172#define PCI_HOST_FORCE 1 /* configure as pci host */
173#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroesed4629c82003-05-23 11:30:39 +0000174
wdenkc837dcb2004-01-20 23:12:12 +0000175#define CONFIG_PCI /* include pci support */
176#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
177#define CONFIG_PCI_PNP /* do pci plug-and-play */
178 /* resource configuration */
stroesed4629c82003-05-23 11:30:39 +0000179
wdenkc837dcb2004-01-20 23:12:12 +0000180#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroesed4629c82003-05-23 11:30:39 +0000181
stroesea20b27a2004-12-16 18:05:42 +0000182#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
183
wdenkc837dcb2004-01-20 23:12:12 +0000184#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
stroesed4629c82003-05-23 11:30:39 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
187#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
188#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
189#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
190#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
191#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
192#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
193#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
194#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
Matthias Fuchs468ebf12012-11-02 14:30:34 +0100195#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
stroesed4629c82003-05-23 11:30:39 +0000196
Matthias Fuchs82379b52009-09-07 17:00:41 +0200197#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
198
stroesed4629c82003-05-23 11:30:39 +0000199/*-----------------------------------------------------------------------
200 * IDE/ATA stuff
201 *-----------------------------------------------------------------------
202 */
wdenkc837dcb2004-01-20 23:12:12 +0000203#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
204#undef CONFIG_IDE_LED /* no led for ide supported */
stroesed4629c82003-05-23 11:30:39 +0000205#define CONFIG_IDE_RESET 1 /* reset for ide supported */
206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
208#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
stroesed4629c82003-05-23 11:30:39 +0000209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
211#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroesed4629c82003-05-23 11:30:39 +0000212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
214#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
215#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesed4629c82003-05-23 11:30:39 +0000216
217/*-----------------------------------------------------------------------
218 * Start addresses for the final memory configuration
219 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesed4629c82003-05-23 11:30:39 +0000221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_SDRAM_BASE 0x00000000
223#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
224#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
225#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
226#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
stroesed4629c82003-05-23 11:30:39 +0000227
Matthias Fuchs3ba605d2009-01-02 12:18:49 +0100228#define CONFIG_PRAM 0 /* use pram variable to overwrite */
229
stroesed4629c82003-05-23 11:30:39 +0000230/*
231 * For booting Linux, the board info and command line data
232 * have to be in the first 8 MB of memory, since this is
233 * the maximum mapped by the Linux kernel during initialization.
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchsac53ee82008-09-05 15:34:04 +0200236
237#define CONFIG_OF_LIBFDT
238#define CONFIG_OF_BOARD_SETUP
239
stroesed4629c82003-05-23 11:30:39 +0000240/*-----------------------------------------------------------------------
241 * FLASH organization
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
244#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesed4629c82003-05-23 11:30:39 +0000245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
247#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
stroesed4629c82003-05-23 11:30:39 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
250#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
251#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesed4629c82003-05-23 11:30:39 +0000252/*
253 * The following defines are added for buggy IOP480 byte interface.
254 * All other boards should use the standard values (CPCI405 etc.)
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
257#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
258#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesed4629c82003-05-23 11:30:39 +0000259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesed4629c82003-05-23 11:30:39 +0000261
stroesed4629c82003-05-23 11:30:39 +0000262/*-----------------------------------------------------------------------
stroese2853d292003-09-12 08:53:54 +0000263 * I2C EEPROM (CAT24WC32) for environment
stroesed4629c82003-05-23 11:30:39 +0000264 */
265#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200266#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
268#define CONFIG_SYS_I2C_SLAVE 0x7F
stroesed4629c82003-05-23 11:30:39 +0000269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
271#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000272/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
274#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */
275#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
stroese2853d292003-09-12 08:53:54 +0000276 /* 32 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000277 /* last 5 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesed4629c82003-05-23 11:30:39 +0000279
stroese2853d292003-09-12 08:53:54 +0000280/* Use EEPROM for environment variables */
281
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200282#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200283#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
284#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
stroese2853d292003-09-12 08:53:54 +0000285 /* total size of a CAT24WC32 is 4096 bytes */
286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
288#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
289#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
stroese2853d292003-09-12 08:53:54 +0000290
stroesed4629c82003-05-23 11:30:39 +0000291/*
292 * Init Memory Controller:
293 *
294 * BR0/1 and OR0/1 (FLASH)
295 */
296
297#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
298#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
299
300/*-----------------------------------------------------------------------
301 * External Bus Controller (EBC) Setup
302 */
303
wdenkc837dcb2004-01-20 23:12:12 +0000304/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_EBC_PB0AP 0x92015480
306#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesed4629c82003-05-23 11:30:39 +0000307
wdenkc837dcb2004-01-20 23:12:12 +0000308/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_EBC_PB1AP 0x92015480
310#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
stroesed4629c82003-05-23 11:30:39 +0000311
wdenkc837dcb2004-01-20 23:12:12 +0000312/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
314#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
315#define CONFIG_SYS_LED_ADDR 0xF0000380
stroesed4629c82003-05-23 11:30:39 +0000316
wdenkc837dcb2004-01-20 23:12:12 +0000317/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
319#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesed4629c82003-05-23 11:30:39 +0000320
wdenkc837dcb2004-01-20 23:12:12 +0000321/* Memory Bank 4 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
323#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
324#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
stroesed4629c82003-05-23 11:30:39 +0000325
wdenkc837dcb2004-01-20 23:12:12 +0000326/* Memory Bank 5 (optional Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
328#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
stroesed4629c82003-05-23 11:30:39 +0000329
wdenkc837dcb2004-01-20 23:12:12 +0000330/* Memory Bank 6 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
332#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
333#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
stroesed4629c82003-05-23 11:30:39 +0000334
335/*-----------------------------------------------------------------------
336 * FPGA stuff
337 */
338/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_FPGA_MODE 0x00
340#define CONFIG_SYS_FPGA_STATUS 0x02
341#define CONFIG_SYS_FPGA_TS 0x04
342#define CONFIG_SYS_FPGA_TS_LOW 0x06
343#define CONFIG_SYS_FPGA_TS_CAP0 0x10
344#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
345#define CONFIG_SYS_FPGA_TS_CAP1 0x14
346#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
347#define CONFIG_SYS_FPGA_TS_CAP2 0x18
348#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
349#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
350#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
stroesed4629c82003-05-23 11:30:39 +0000351
352/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
354#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
355#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
356#define CONFIG_SYS_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */
357#define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR 0x0200
358#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
359#define CONFIG_SYS_FPGA_MODE_1WIRE 0x1000
360#define CONFIG_SYS_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */
361#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL 0x4000
stroesed4629c82003-05-23 11:30:39 +0000362
363/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
365#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
366#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
367#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
368#define CONFIG_SYS_FPGA_STATUS_1WIRE 0x1000
369#define CONFIG_SYS_FPGA_STATUS_SIM_OK 0x2000
stroesed4629c82003-05-23 11:30:39 +0000370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
372#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */
stroesed4629c82003-05-23 11:30:39 +0000373
374/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
376#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
377#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
378#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
379#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesed4629c82003-05-23 11:30:39 +0000380
381/*-----------------------------------------------------------------------
382 * Definitions for initial stack pointer and data area (in data cache)
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
stroesed4629c82003-05-23 11:30:39 +0000385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200387#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200388#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesed4629c82003-05-23 11:30:39 +0000390
stroesed4629c82003-05-23 11:30:39 +0000391#endif /* __CONFIG_H */