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wdenk983fda82004-10-28 00:09:35 +00001/*
2 * dramSetup.h
3 *
4 * Prototypes, etc. for the Motorola MPC8220
5 * embedded cpu chips
6 *
7 * 2004 (c) Freescale, Inc.
8 * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28#ifndef __INCdramsetuph
29#define __INCdramsetuph
30#ifndef __ASSEMBLY__
31/* Where various things are in the SPD */
32#define LOC_TYPE 2
33#define LOC_CHECKSUM 63
34#define LOC_PHYS_BANKS 5
35#define LOC_LOGICAL_BANKS 17
36#define LOC_ROWS 3
37#define LOC_COLS 4
38#define LOC_WIDTH_HIGH 7
39#define LOC_WIDTH_LOW 6
40#define LOC_REFRESH 12
41#define LOC_BURSTS 16
42#define LOC_CAS 18
43#define LOC_CS 19
44#define LOC_WE 20
45#define LOC_Tcyc 9
46#define LOC_Tac 10
47#define LOC_Trp 27
48#define LOC_Trrd 28
49#define LOC_Trcd 29
50#define LOC_Tras 30
51#define LOC_Buffered 21
52/* Types of memory the SPD can tell us about.
53 * We can actually only use SDRAM and DDR.
54 */
55#define TYPE_DRAM 1 /* plain old dram */
56#define TYPE_EDO 2 /* EDO dram */
57#define TYPE_Nibble 3 /* serial nibble memory */
58#define TYPE_SDR 4 /* SDRAM */
59#define TYPE_ROM 5 /* */
60#define TYPE_SGRRAM 6 /* graphics memory */
61#define TYPE_DDR 7 /* DDR sdram */
62#define SDRAMDS_MASK 0x3 /* each field is 2 bits wide */
63#define SDRAMDS_SBE_SHIFT 8 /* Clock enable drive strength */
64#define SDRAMDS_SBC_SHIFT 6 /* Clocks drive strength */
65#define SDRAMDS_SBA_SHIFT 4 /* Address drive strength */
66#define SDRAMDS_SBS_SHIFT 2 /* SDR DQS drive strength */
67#define SDRAMDS_SBD_SHIFT 0 /* Data and DQS drive strength */
68#define DRIVE_STRENGTH_HIGH 0
69#define DRIVE_STRENGTH_MED 1
70#define DRIVE_STRENGTH_LOW 2
71#define DRIVE_STRENGTH_OFF 3
72
73#define OK 0
74#define ERROR -1
75/* Structure to hold information about address muxing. */
76 typedef struct tagMuxDescriptor {
77 u8 MuxValue;
78 u8 Columns;
79 u8 Rows;
80 u8 MoreColumns;
81} muxdesc_t;
82
83/* Structure to define one physical bank of
84 * memory. Note that dram size in bytes is
85 * (2^^(rows+columns)) * width * banks / 8
86*/
87typedef struct tagDramInfo {
88 u32 size; /* size in bytes */
89 u32 base; /* base address */
90 u8 ordinal; /* where in the memory map will we put this */
91 u8 type;
92 u8 rows;
93 u8 cols;
94 u16 width; /* width of each chip in bits */
95 u8 banks; /* number of chips, aka logical banks */
96 u8 bursts; /* bit-encoded allowable burst length */
97 u8 CAS; /* bit-encoded CAS latency values */
98 u8 CS; /* bit-encoded CS latency values */
99 u8 WE; /* bit-encoded WE latency values */
100 u8 Trp; /* bit-encoded row precharge time */
101 u8 Trcd; /* bit-encoded RAS to CAS delay */
102 u8 buffered; /* buffered or not */
103 u8 refresh; /* encoded refresh rate */
104} draminfo_t;
105
106#endif /* __ASSEMBLY__ */
107
108#endif /* __INCdramsetuph */