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Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR X11
Mingkai Hudd029362016-09-07 18:47:28 +08002/*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright (C) 2016, Freescale Semiconductor
6 *
7 * Mingkai Hu <mingkai.hu@nxp.com>
Mingkai Hudd029362016-09-07 18:47:28 +08008 */
9
10/include/ "skeleton64.dtsi"
11
12/ {
13 compatible = "fsl,ls1046a";
14 interrupt-parent = <&gic>;
15
16 sysclk: sysclk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
21 };
22
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
25 #interrupt-cells = <3>;
26 interrupt-controller;
27 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
28 <0x0 0x1420000 0 0x10000>, /* GICC */
29 <0x0 0x1440000 0 0x20000>, /* GICH */
30 <0x0 0x1460000 0 0x20000>; /* GICV */
31 interrupts = <1 9 0xf08>;
32 };
33
Madalin Bucur8de63012020-04-23 16:25:15 +030034 soc: soc {
Mingkai Hudd029362016-09-07 18:47:28 +080035 compatible = "simple-bus";
36 #address-cells = <2>;
37 #size-cells = <2>;
38 ranges;
39
40 clockgen: clocking@1ee1000 {
41 compatible = "fsl,ls1046a-clockgen";
42 reg = <0x0 0x1ee1000 0x0 0x1000>;
43 #clock-cells = <2>;
44 clocks = <&sysclk>;
45 };
46
47 dspi0: dspi@2100000 {
48 compatible = "fsl,vf610-dspi";
49 #address-cells = <1>;
50 #size-cells = <0>;
51 reg = <0x0 0x2100000 0x0 0x10000>;
52 interrupts = <0 64 0x4>;
53 clock-names = "dspi";
54 clocks = <&clockgen 4 0>;
Michael Walle8c580892021-10-13 18:14:18 +020055 spi-num-chipselects = <6>;
Mingkai Hudd029362016-09-07 18:47:28 +080056 big-endian;
57 status = "disabled";
58 };
59
60 dspi1: dspi@2110000 {
61 compatible = "fsl,vf610-dspi";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 reg = <0x0 0x2110000 0x0 0x10000>;
65 interrupts = <0 65 0x4>;
66 clock-names = "dspi";
67 clocks = <&clockgen 4 0>;
Michael Walle8c580892021-10-13 18:14:18 +020068 spi-num-chipselects = <6>;
Mingkai Hudd029362016-09-07 18:47:28 +080069 big-endian;
70 status = "disabled";
71 };
72
Yinbo Zhu2fd425f2018-09-25 14:47:11 +080073 esdhc: esdhc@1560000 {
74 compatible = "fsl,esdhc";
75 reg = <0x0 0x1560000 0x0 0x10000>;
76 interrupts = <0 62 0x4>;
77 big-endian;
78 bus-width = <4>;
79 };
80
Biwen Lib7ddedf2021-02-05 19:01:52 +080081 gpio0: gpio@2300000 {
82 compatible = "fsl,qoriq-gpio";
83 reg = <0x0 0x2300000 0x0 0x10000>;
84 interrupts = <0 66 4>;
85 gpio-controller;
86 #gpio-cells = <2>;
87 interrupt-controller;
88 #interrupt-cells = <2>;
89 };
90
91 gpio1: gpio@2310000 {
92 compatible = "fsl,qoriq-gpio";
93 reg = <0x0 0x2310000 0x0 0x10000>;
94 interrupts = <0 67 4>;
95 gpio-controller;
96 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <2>;
99 };
100
101 gpio2: gpio@2320000 {
102 compatible = "fsl,qoriq-gpio";
103 reg = <0x0 0x2320000 0x0 0x10000>;
104 interrupts = <0 68 4>;
105 gpio-controller;
106 #gpio-cells = <2>;
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 };
110
111 gpio3: gpio@2330000 {
112 compatible = "fsl,qoriq-gpio";
113 reg = <0x0 0x2330000 0x0 0x10000>;
114 interrupts = <0 134 4>;
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
Mingkai Hudd029362016-09-07 18:47:28 +0800121 ifc: ifc@1530000 {
122 compatible = "fsl,ifc", "simple-bus";
123 reg = <0x0 0x1530000 0x0 0x10000>;
124 interrupts = <0 43 0x4>;
125 };
126
127 i2c0: i2c@2180000 {
128 compatible = "fsl,vf610-i2c";
129 #address-cells = <1>;
130 #size-cells = <0>;
131 reg = <0x0 0x2180000 0x0 0x10000>;
132 interrupts = <0 56 0x4>;
133 clock-names = "i2c";
134 clocks = <&clockgen 4 0>;
135 status = "disabled";
136 };
137
138 i2c1: i2c@2190000 {
139 compatible = "fsl,vf610-i2c";
140 #address-cells = <1>;
141 #size-cells = <0>;
142 reg = <0x0 0x2190000 0x0 0x10000>;
143 interrupts = <0 57 0x4>;
144 clock-names = "i2c";
145 clocks = <&clockgen 4 0>;
146 status = "disabled";
147 };
148
149 i2c2: i2c@21a0000 {
150 compatible = "fsl,vf610-i2c";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 reg = <0x0 0x21a0000 0x0 0x10000>;
154 interrupts = <0 58 0x4>;
155 clock-names = "i2c";
156 clocks = <&clockgen 4 0>;
157 status = "disabled";
158 };
159
160 i2c3: i2c@21b0000 {
161 compatible = "fsl,vf610-i2c";
162 #address-cells = <1>;
163 #size-cells = <0>;
164 reg = <0x0 0x21b0000 0x0 0x10000>;
165 interrupts = <0 59 0x4>;
166 clock-names = "i2c";
167 clocks = <&clockgen 4 0>;
168 status = "disabled";
169 };
170
171 duart0: serial@21c0500 {
172 compatible = "fsl,ns16550", "ns16550a";
173 reg = <0x00 0x21c0500 0x0 0x100>;
174 interrupts = <0 54 0x4>;
175 clocks = <&clockgen 4 0>;
176 };
177
178 duart1: serial@21c0600 {
179 compatible = "fsl,ns16550", "ns16550a";
180 reg = <0x00 0x21c0600 0x0 0x100>;
181 interrupts = <0 54 0x4>;
182 clocks = <&clockgen 4 0>;
183 };
184
185 duart2: serial@21d0500 {
186 compatible = "fsl,ns16550", "ns16550a";
187 reg = <0x0 0x21d0500 0x0 0x100>;
188 interrupts = <0 55 0x4>;
189 clocks = <&clockgen 4 0>;
190 };
191
192 duart3: serial@21d0600 {
193 compatible = "fsl,ns16550", "ns16550a";
194 reg = <0x0 0x21d0600 0x0 0x100>;
195 interrupts = <0 55 0x4>;
196 clocks = <&clockgen 4 0>;
197 };
198
Shaohui Xiefdc2b542016-10-28 14:24:02 +0800199 lpuart0: serial@2950000 {
200 compatible = "fsl,ls1021a-lpuart";
201 reg = <0x0 0x2950000 0x0 0x1000>;
202 interrupts = <0 48 0x4>;
203 clocks = <&clockgen 4 0>;
204 clock-names = "ipg";
205 status = "disabled";
206 };
207
208 lpuart1: serial@2960000 {
209 compatible = "fsl,ls1021a-lpuart";
210 reg = <0x0 0x2960000 0x0 0x1000>;
211 interrupts = <0 49 0x4>;
212 clocks = <&clockgen 4 1>;
213 clock-names = "ipg";
214 status = "disabled";
215 };
216
217 lpuart2: serial@2970000 {
218 compatible = "fsl,ls1021a-lpuart";
219 reg = <0x0 0x2970000 0x0 0x1000>;
220 interrupts = <0 50 0x4>;
221 clocks = <&clockgen 4 1>;
222 clock-names = "ipg";
223 status = "disabled";
224 };
225
226 lpuart3: serial@2980000 {
227 compatible = "fsl,ls1021a-lpuart";
228 reg = <0x0 0x2980000 0x0 0x1000>;
229 interrupts = <0 51 0x4>;
230 clocks = <&clockgen 4 1>;
231 clock-names = "ipg";
232 status = "disabled";
233 };
234
235 lpuart4: serial@2990000 {
236 compatible = "fsl,ls1021a-lpuart";
237 reg = <0x0 0x2990000 0x0 0x1000>;
238 interrupts = <0 52 0x4>;
239 clocks = <&clockgen 4 1>;
240 clock-names = "ipg";
241 status = "disabled";
242 };
243
244 lpuart5: serial@29a0000 {
245 compatible = "fsl,ls1021a-lpuart";
246 reg = <0x0 0x29a0000 0x0 0x1000>;
247 interrupts = <0 53 0x4>;
248 clocks = <&clockgen 4 1>;
249 clock-names = "ipg";
250 status = "disabled";
251 };
252
Mingkai Hudd029362016-09-07 18:47:28 +0800253 qspi: quadspi@1550000 {
Kuldeep Singhb480bcc2019-12-12 11:49:24 +0530254 compatible = "fsl,ls1021a-qspi";
Mingkai Hudd029362016-09-07 18:47:28 +0800255 #address-cells = <1>;
256 #size-cells = <0>;
257 reg = <0x0 0x1550000 0x0 0x10000>,
258 <0x0 0x40000000 0x0 0x10000000>;
259 reg-names = "QuadSPI", "QuadSPI-memory";
Mingkai Hudd029362016-09-07 18:47:28 +0800260 status = "disabled";
261 };
Minghuan Lianb948a162016-12-13 14:54:14 +0800262
Tang Yuantian272a24f2017-01-20 17:12:48 +0800263 usb0: usb@2f00000 {
264 compatible = "fsl,layerscape-dwc3";
265 reg = <0x0 0x2f00000 0x0 0x10000>;
266 interrupts = <0 60 4>;
267 dr_mode = "host";
268 };
269
270 usb1: usb@3000000 {
271 compatible = "fsl,layerscape-dwc3";
272 reg = <0x0 0x3000000 0x0 0x10000>;
273 interrupts = <0 61 4>;
274 dr_mode = "host";
275 };
276
277 usb2: usb@3100000 {
278 compatible = "fsl,layerscape-dwc3";
279 reg = <0x0 0x3100000 0x0 0x10000>;
280 interrupts = <0 63 4>;
281 dr_mode = "host";
282 };
283
Wasim Khan2adb7972020-09-28 16:26:07 +0530284 pcie1: pcie@3400000 {
Minghuan Lianb948a162016-12-13 14:54:14 +0800285 compatible = "fsl,ls-pcie", "snps,dw-pcie";
286 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
287 0x00 0x03480000 0x0 0x40000 /* lut registers */
288 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
289 0x40 0x00000000 0x0 0x20000>; /* configuration space */
290 reg-names = "dbi", "lut", "ctrl", "config";
291 big-endian;
292 #address-cells = <3>;
293 #size-cells = <2>;
294 device_type = "pci";
295 bus-range = <0x0 0xff>;
296 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
297 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
298 };
299
Wasim Khan2adb7972020-09-28 16:26:07 +0530300 pcie_ep1: pcie_ep@3400000 {
Xiaowei Bao57fcc132020-07-09 23:31:35 +0800301 compatible = "fsl,ls-pcie-ep";
302 reg = <0x00 0x03400000 0x0 0x80000
303 0x00 0x034c0000 0x0 0x40000
304 0x40 0x00000000 0x8 0x00000000>;
305 reg-names = "regs", "ctrl", "addr_space";
306 num-ib-windows = <6>;
307 num-ob-windows = <8>;
308 big-endian;
309 };
310
Wasim Khan2adb7972020-09-28 16:26:07 +0530311 pcie2: pcie@3500000 {
Minghuan Lianb948a162016-12-13 14:54:14 +0800312 compatible = "fsl,ls-pcie", "snps,dw-pcie";
313 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
314 0x00 0x03580000 0x0 0x40000 /* lut registers */
315 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
316 0x48 0x00000000 0x0 0x20000>; /* configuration space */
317 reg-names = "dbi", "lut", "ctrl", "config";
318 big-endian;
319 #address-cells = <3>;
320 #size-cells = <2>;
321 device_type = "pci";
322 num-lanes = <2>;
323 bus-range = <0x0 0xff>;
324 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
325 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
326 };
327
Wasim Khan2adb7972020-09-28 16:26:07 +0530328 pcie_ep2: pcie_ep@3500000 {
Xiaowei Bao57fcc132020-07-09 23:31:35 +0800329 compatible = "fsl,ls-pcie-ep";
330 reg = <0x00 0x03500000 0x0 0x80000
331 0x00 0x035c0000 0x0 0x40000
332 0x48 0x00000000 0x8 0x00000000>;
333 reg-names = "regs", "ctrl", "addr_space";
334 num-ib-windows = <6>;
335 num-ob-windows = <8>;
336 big-endian;
337 };
338
Wasim Khan2adb7972020-09-28 16:26:07 +0530339 pcie3: pcie@3600000 {
Minghuan Lianb948a162016-12-13 14:54:14 +0800340 compatible = "fsl,ls-pcie", "snps,dw-pcie";
341 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
342 0x00 0x03680000 0x0 0x40000 /* lut registers */
343 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
344 0x50 0x00000000 0x0 0x20000>; /* configuration space */
345 reg-names = "dbi", "lut", "ctrl", "config";
346 big-endian;
347 #address-cells = <3>;
348 #size-cells = <2>;
349 device_type = "pci";
350 bus-range = <0x0 0xff>;
351 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
352 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
353 };
Peng Ma539e0cb2018-10-11 10:34:20 +0000354
Wasim Khan2adb7972020-09-28 16:26:07 +0530355 pcie_ep3: pcie_ep@3600000 {
Xiaowei Bao57fcc132020-07-09 23:31:35 +0800356 compatible = "fsl,ls-pcie-ep";
357 reg = <0x00 0x03600000 0x0 0x80000
358 0x00 0x036c0000 0x0 0x40000
359 0x50 0x00000000 0x8 0x00000000>;
360 reg-names = "regs", "ctrl", "addr_space";
361 num-ib-windows = <6>;
362 num-ob-windows = <8>;
363 big-endian;
364 };
365
Peng Ma539e0cb2018-10-11 10:34:20 +0000366 sata: sata@3200000 {
367 compatible = "fsl,ls1046a-ahci";
Peng Mae765ee52019-04-17 10:10:49 +0000368 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
369 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
Michael Wallecde9b142021-10-13 18:14:20 +0200370 reg-names = "ahci", "sata-ecc";
Peng Ma539e0cb2018-10-11 10:34:20 +0000371 interrupts = <0 69 4>;
372 clocks = <&clockgen 4 1>;
373 status = "disabled";
374 };
Mingkai Hudd029362016-09-07 18:47:28 +0800375 };
376};