blob: 99b9cef17c29ecf73ef3b844474a5b196f29eeff [file] [log] [blame]
Dirk Behme12201a12008-12-14 09:47:16 +01001/*
2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/errno.h>
27#include <asm/arch/mem.h>
28#include <asm/arch/omap_gpmc.h>
29#include <linux/mtd/nand_ecc.h>
30#include <nand.h>
31
32static uint8_t cs;
Dirk Behme12201a12008-12-14 09:47:16 +010033static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
34
35/*
36 * omap_nand_hwcontrol - Set the address pointers corretly for the
37 * following address/data/command operation
38 */
39static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
40 uint32_t ctrl)
41{
42 register struct nand_chip *this = mtd->priv;
43
44 /*
45 * Point the IO_ADDR to DATA and ADDRESS registers instead
46 * of chip address
47 */
48 switch (ctrl) {
49 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
Dirk Behme89411352009-08-08 09:30:22 +020050 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
Dirk Behme12201a12008-12-14 09:47:16 +010051 break;
52 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
Dirk Behme89411352009-08-08 09:30:22 +020053 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
Dirk Behme12201a12008-12-14 09:47:16 +010054 break;
55 case NAND_CTRL_CHANGE | NAND_NCE:
Dirk Behme89411352009-08-08 09:30:22 +020056 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
Dirk Behme12201a12008-12-14 09:47:16 +010057 break;
58 }
59
60 if (cmd != NAND_CMD_NONE)
61 writeb(cmd, this->IO_ADDR_W);
62}
63
64/*
65 * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
66 * GPMC controller
67 * @mtd: MTD device structure
68 *
69 */
70static void omap_hwecc_init(struct nand_chip *chip)
71{
72 /*
73 * Init ECC Control Register
74 * Clear all ECC | Enable Reg1
75 */
Dirk Behme89411352009-08-08 09:30:22 +020076 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
77 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
Dirk Behme12201a12008-12-14 09:47:16 +010078}
79
80/*
81 * gen_true_ecc - This function will generate true ECC value, which
82 * can be used when correcting data read from NAND flash memory core
83 *
84 * @ecc_buf: buffer to store ecc code
85 *
86 * @return: re-formatted ECC value
87 */
88static uint32_t gen_true_ecc(uint8_t *ecc_buf)
89{
90 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
91 ((ecc_buf[2] & 0x0F) << 8);
92}
93
94/*
95 * omap_correct_data - Compares the ecc read from nand spare area with ECC
96 * registers values and corrects one bit error if it has occured
97 * Further details can be had from OMAP TRM and the following selected links:
98 * http://en.wikipedia.org/wiki/Hamming_code
99 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
100 *
101 * @mtd: MTD device structure
102 * @dat: page data
103 * @read_ecc: ecc read from nand flash
104 * @calc_ecc: ecc read from ECC registers
105 *
106 * @return 0 if data is OK or corrected, else returns -1
107 */
108static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
109 uint8_t *read_ecc, uint8_t *calc_ecc)
110{
111 uint32_t orig_ecc, new_ecc, res, hm;
112 uint16_t parity_bits, byte;
113 uint8_t bit;
114
115 /* Regenerate the orginal ECC */
116 orig_ecc = gen_true_ecc(read_ecc);
117 new_ecc = gen_true_ecc(calc_ecc);
118 /* Get the XOR of real ecc */
119 res = orig_ecc ^ new_ecc;
120 if (res) {
121 /* Get the hamming width */
122 hm = hweight32(res);
123 /* Single bit errors can be corrected! */
124 if (hm == 12) {
125 /* Correctable data! */
126 parity_bits = res >> 16;
127 bit = (parity_bits & 0x7);
128 byte = (parity_bits >> 3) & 0x1FF;
129 /* Flip the bit to correct */
130 dat[byte] ^= (0x1 << bit);
131 } else if (hm == 1) {
132 printf("Error: Ecc is wrong\n");
133 /* ECC itself is corrupted */
134 return 2;
135 } else {
136 /*
137 * hm distance != parity pairs OR one, could mean 2 bit
138 * error OR potentially be on a blank page..
139 * orig_ecc: contains spare area data from nand flash.
140 * new_ecc: generated ecc while reading data area.
141 * Note: if the ecc = 0, all data bits from which it was
142 * generated are 0xFF.
143 * The 3 byte(24 bits) ecc is generated per 512byte
144 * chunk of a page. If orig_ecc(from spare area)
145 * is 0xFF && new_ecc(computed now from data area)=0x0,
146 * this means that data area is 0xFF and spare area is
147 * 0xFF. A sure sign of a erased page!
148 */
149 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
150 return 0;
151 printf("Error: Bad compare! failed\n");
152 /* detected 2 bit error */
153 return -1;
154 }
155 }
156 return 0;
157}
158
159/*
160 * omap_calculate_ecc - Generate non-inverted ECC bytes.
161 *
162 * Using noninverted ECC can be considered ugly since writing a blank
163 * page ie. padding will clear the ECC bytes. This is no problem as
164 * long nobody is trying to write data on the seemingly unused page.
165 * Reading an erased page will produce an ECC mismatch between
166 * generated and read ECC bytes that has to be dealt with separately.
167 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
168 * is used, the result of read will be 0x0 while the ECC offsets of the
169 * spare area will be 0xFF which will result in an ECC mismatch.
170 * @mtd: MTD structure
171 * @dat: unused
172 * @ecc_code: ecc_code buffer
173 */
174static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
175 uint8_t *ecc_code)
176{
177 u_int32_t val;
178
179 /* Start Reading from HW ECC1_Result = 0x200 */
Dirk Behme89411352009-08-08 09:30:22 +0200180 val = readl(&gpmc_cfg->ecc1_result);
Dirk Behme12201a12008-12-14 09:47:16 +0100181
182 ecc_code[0] = val & 0xFF;
183 ecc_code[1] = (val >> 16) & 0xFF;
184 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
185
186 /*
187 * Stop reading anymore ECC vals and clear old results
188 * enable will be called if more reads are required
189 */
Dirk Behme89411352009-08-08 09:30:22 +0200190 writel(0x000, &gpmc_cfg->ecc_config);
Dirk Behme12201a12008-12-14 09:47:16 +0100191
192 return 0;
193}
194
195/*
196 * omap_enable_ecc - This function enables the hardware ecc functionality
197 * @mtd: MTD device structure
198 * @mode: Read/Write mode
199 */
200static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
201{
202 struct nand_chip *chip = mtd->priv;
203 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
204
205 switch (mode) {
206 case NAND_ECC_READ:
207 case NAND_ECC_WRITE:
208 /* Clear the ecc result registers, select ecc reg as 1 */
Dirk Behme89411352009-08-08 09:30:22 +0200209 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
Dirk Behme12201a12008-12-14 09:47:16 +0100210
211 /*
212 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
213 * tell all regs to generate size0 sized regs
214 * we just have a single ECC engine for all CS
215 */
216 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
Dirk Behme89411352009-08-08 09:30:22 +0200217 &gpmc_cfg->ecc_size_config);
Dirk Behme12201a12008-12-14 09:47:16 +0100218 val = (dev_width << 7) | (cs << 1) | (0x1);
Dirk Behme89411352009-08-08 09:30:22 +0200219 writel(val, &gpmc_cfg->ecc_config);
Dirk Behme12201a12008-12-14 09:47:16 +0100220 break;
221 default:
222 printf("Error: Unrecognized Mode[%d]!\n", mode);
223 break;
224 }
225}
226
227/*
228 * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
229 * The default is to come up on s/w ecc
230 *
231 * @hardware - 1 -switch to h/w ecc, 0 - s/w ecc
232 *
233 */
234void omap_nand_switch_ecc(int32_t hardware)
235{
236 struct nand_chip *nand;
237 struct mtd_info *mtd;
238
239 if (nand_curr_device < 0 ||
240 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
241 !nand_info[nand_curr_device].name) {
242 printf("Error: Can't switch ecc, no devices available\n");
243 return;
244 }
245
246 mtd = &nand_info[nand_curr_device];
247 nand = mtd->priv;
248
249 nand->options |= NAND_OWN_BUFFERS;
250
251 /* Reset ecc interface */
252 nand->ecc.read_page = NULL;
253 nand->ecc.write_page = NULL;
254 nand->ecc.read_oob = NULL;
255 nand->ecc.write_oob = NULL;
256 nand->ecc.hwctl = NULL;
257 nand->ecc.correct = NULL;
258 nand->ecc.calculate = NULL;
259
260 /* Setup the ecc configurations again */
261 if (hardware) {
262 nand->ecc.mode = NAND_ECC_HW;
263 nand->ecc.layout = &hw_nand_oob;
264 nand->ecc.size = 512;
265 nand->ecc.bytes = 3;
266 nand->ecc.hwctl = omap_enable_hwecc;
267 nand->ecc.correct = omap_correct_data;
268 nand->ecc.calculate = omap_calculate_ecc;
269 omap_hwecc_init(nand);
270 printf("HW ECC selected\n");
271 } else {
272 nand->ecc.mode = NAND_ECC_SOFT;
273 /* Use mtd default settings */
274 nand->ecc.layout = NULL;
275 printf("SW ECC selected\n");
276 }
277
278 /* Update NAND handling after ECC mode switch */
279 nand_scan_tail(mtd);
280
281 nand->options &= ~NAND_OWN_BUFFERS;
282}
283
284/*
285 * Board-specific NAND initialization. The following members of the
286 * argument are board-specific:
287 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
288 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
289 * - cmd_ctrl: hardwarespecific function for accesing control-lines
290 * - waitfunc: hardwarespecific function for accesing device ready/busy line
291 * - ecc.hwctl: function to enable (reset) hardware ecc generator
292 * - ecc.mode: mode of ecc, see defines
293 * - chip_delay: chip dependent delay for transfering data from array to
294 * read regs (tR)
295 * - options: various chip options. They can partly be set to inform
296 * nand_scan about special functionality. See the defines for further
297 * explanation
298 */
299int board_nand_init(struct nand_chip *nand)
300{
301 int32_t gpmc_config = 0;
302 cs = 0;
303
304 /*
305 * xloader/Uboot's gpmc configuration would have configured GPMC for
306 * nand type of memory. The following logic scans and latches on to the
307 * first CS with NAND type memory.
308 * TBD: need to make this logic generic to handle multiple CS NAND
309 * devices.
310 */
311 while (cs < GPMC_MAX_CS) {
Dirk Behme12201a12008-12-14 09:47:16 +0100312 /* Check if NAND type is set */
Dirk Behme89411352009-08-08 09:30:22 +0200313 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
Dirk Behme12201a12008-12-14 09:47:16 +0100314 /* Found it!! */
315 break;
316 }
317 cs++;
318 }
319 if (cs >= GPMC_MAX_CS) {
320 printf("NAND: Unable to find NAND settings in "
321 "GPMC Configuration - quitting\n");
322 return -ENODEV;
323 }
324
Dirk Behme89411352009-08-08 09:30:22 +0200325 gpmc_config = readl(&gpmc_cfg->config);
Dirk Behme12201a12008-12-14 09:47:16 +0100326 /* Disable Write protect */
327 gpmc_config |= 0x10;
Dirk Behme89411352009-08-08 09:30:22 +0200328 writel(gpmc_config, &gpmc_cfg->config);
Dirk Behme12201a12008-12-14 09:47:16 +0100329
Dirk Behme89411352009-08-08 09:30:22 +0200330 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
331 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
Dirk Behme12201a12008-12-14 09:47:16 +0100332
333 nand->cmd_ctrl = omap_nand_hwcontrol;
334 nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
335 /* If we are 16 bit dev, our gpmc config tells us that */
Dirk Behme89411352009-08-08 09:30:22 +0200336 if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
Dirk Behme12201a12008-12-14 09:47:16 +0100337 nand->options |= NAND_BUSWIDTH_16;
338
339 nand->chip_delay = 100;
340 /* Default ECC mode */
341 nand->ecc.mode = NAND_ECC_SOFT;
342
343 return 0;
344}