blob: 48bfcd4f3406d7eb24edc239c36ffe5c79c62026 [file] [log] [blame]
Simon Glass7b7ad5c2016-01-21 19:45:05 -07001/*
2 * Copyright (c) 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <display.h>
11#include <dm.h>
12#include <edid.h>
13#include <regmap.h>
14#include <syscon.h>
15#include <video.h>
16#include <asm/gpio.h>
17#include <asm/hardware.h>
18#include <asm/io.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/cru_rk3288.h>
21#include <asm/arch/grf_rk3288.h>
22#include <asm/arch/edp_rk3288.h>
Simon Glass7b7ad5c2016-01-21 19:45:05 -070023#include <asm/arch/vop_rk3288.h>
24#include <dm/device-internal.h>
25#include <dm/uclass-internal.h>
26#include <dt-bindings/clock/rk3288-cru.h>
27#include <power/regulator.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31struct rk_vop_priv {
32 struct rk3288_vop *regs;
33 struct rk3288_grf *grf;
34};
35
36void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
37 int fb_bits_per_pixel, const struct display_timing *edid)
38{
39 u32 lb_mode;
40 u32 rgb_mode;
41 u32 hactive = edid->hactive.typ;
42 u32 vactive = edid->vactive.typ;
43
44 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
45 &regs->win0_act_info);
46
47 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
48 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
49 &regs->win0_dsp_st);
50
51 writel(V_DSP_WIDTH(hactive - 1) |
52 V_DSP_HEIGHT(vactive - 1),
53 &regs->win0_dsp_info);
54
55 clrsetbits_le32(&regs->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
56 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
57
58 switch (fb_bits_per_pixel) {
59 case 16:
60 rgb_mode = RGB565;
61 writel(V_RGB565_VIRWIDTH(hactive), &regs->win0_vir);
62 break;
63 case 24:
64 rgb_mode = RGB888;
65 writel(V_RGB888_VIRWIDTH(hactive), &regs->win0_vir);
66 break;
67 case 32:
68 default:
69 rgb_mode = ARGB8888;
70 writel(V_ARGB888_VIRWIDTH(hactive), &regs->win0_vir);
71 break;
72 }
73
74 if (hactive > 2560)
75 lb_mode = LB_RGB_3840X2;
76 else if (hactive > 1920)
77 lb_mode = LB_RGB_2560X4;
78 else if (hactive > 1280)
79 lb_mode = LB_RGB_1920X5;
80 else
81 lb_mode = LB_RGB_1280X8;
82
83 clrsetbits_le32(&regs->win0_ctrl0,
84 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
85 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
86 V_WIN0_EN(1));
87
88 writel(fbbase, &regs->win0_yrgb_mst);
89 writel(0x01, &regs->reg_cfg_done); /* enable reg config */
90}
91
92void rkvop_mode_set(struct rk3288_vop *regs,
93 const struct display_timing *edid, enum vop_modes mode)
94{
95 u32 hactive = edid->hactive.typ;
96 u32 vactive = edid->vactive.typ;
97 u32 hsync_len = edid->hsync_len.typ;
98 u32 hback_porch = edid->hback_porch.typ;
99 u32 vsync_len = edid->vsync_len.typ;
100 u32 vback_porch = edid->vback_porch.typ;
101 u32 hfront_porch = edid->hfront_porch.typ;
102 u32 vfront_porch = edid->vfront_porch.typ;
103 uint flags;
Jacob Chen85307832016-03-14 11:20:18 +0800104 int mode_flags;
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700105
106 switch (mode) {
107 case VOP_MODE_HDMI:
108 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
109 V_HDMI_OUT_EN(1));
110 break;
111 case VOP_MODE_EDP:
112 default:
113 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
114 V_EDP_OUT_EN(1));
115 break;
Jacob Chen85307832016-03-14 11:20:18 +0800116 case VOP_MODE_LVDS:
117 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
118 V_RGB_OUT_EN(1));
119 break;
Eric Gao9f819932017-05-02 18:23:52 +0800120 case VOP_MODE_MIPI:
121 clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
122 V_MIPI_OUT_EN(1));
123 break;
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700124 }
125
Jacob Chen85307832016-03-14 11:20:18 +0800126 if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
127 /* RGBaaa */
128 mode_flags = 15;
129 else
130 /* RGB888 */
131 mode_flags = 0;
132
133 flags = V_DSP_OUT_MODE(mode_flags) |
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700134 V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) |
135 V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH));
136
137 clrsetbits_le32(&regs->dsp_ctrl0,
138 M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
139 flags);
140
141 writel(V_HSYNC(hsync_len) |
142 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
143 &regs->dsp_htotal_hs_end);
144
145 writel(V_HEAP(hsync_len + hback_porch + hactive) |
146 V_HASP(hsync_len + hback_porch),
147 &regs->dsp_hact_st_end);
148
149 writel(V_VSYNC(vsync_len) |
150 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
151 &regs->dsp_vtotal_vs_end);
152
153 writel(V_VAEP(vsync_len + vback_porch + vactive)|
154 V_VASP(vsync_len + vback_porch),
155 &regs->dsp_vact_st_end);
156
157 writel(V_HEAP(hsync_len + hback_porch + hactive) |
158 V_HASP(hsync_len + hback_porch),
159 &regs->post_dsp_hact_info);
160
161 writel(V_VAEP(vsync_len + vback_porch + vactive)|
162 V_VASP(vsync_len + vback_porch),
163 &regs->post_dsp_vact_info);
164
165 writel(0x01, &regs->reg_cfg_done); /* enable reg config */
166}
167
168/**
169 * rk_display_init() - Try to enable the given display device
170 *
171 * This function performs many steps:
172 * - Finds the display device being referenced by @ep_node
173 * - Puts the VOP's ID into its uclass platform data
174 * - Probes the device to set it up
175 * - Reads the EDID timing information
176 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
177 * - Enables the display (the display device handles this and will do different
178 * things depending on the display type)
179 * - Tells the uclass about the display resolution so that the console will
180 * appear correctly
181 *
182 * @dev: VOP device that we want to connect to the display
183 * @fbbase: Frame buffer address
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700184 * @ep_node: Device tree node to process - this is the offset of an endpoint
185 * node within the VOP's 'port' list.
186 * @return 0 if OK, -ve if something went wrong
187 */
Eric Gao8aed0d72017-05-02 18:23:53 +0800188int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700189{
190 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
191 const void *blob = gd->fdt_blob;
192 struct rk_vop_priv *priv = dev_get_priv(dev);
193 int vop_id, remote_vop_id;
194 struct rk3288_vop *regs = priv->regs;
195 struct display_timing timing;
196 struct udevice *disp;
197 int ret, remote, i, offset;
198 struct display_plat *disp_uc_plat;
Stephen Warren135aa952016-06-17 09:44:00 -0600199 struct clk clk;
Eric Gao8aed0d72017-05-02 18:23:53 +0800200 enum video_log2_bpp l2bpp;
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700201
202 vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
203 debug("vop_id=%d\n", vop_id);
204 remote = fdtdec_lookup_phandle(blob, ep_node, "remote-endpoint");
205 if (remote < 0)
206 return -EINVAL;
207 remote_vop_id = fdtdec_get_int(blob, remote, "reg", -1);
208 debug("remote vop_id=%d\n", remote_vop_id);
209
210 for (i = 0, offset = remote; i < 3 && offset > 0; i++)
211 offset = fdt_parent_offset(blob, offset);
212 if (offset < 0) {
213 debug("%s: Invalid remote-endpoint position\n", dev->name);
214 return -EINVAL;
215 }
216
217 ret = uclass_find_device_by_of_offset(UCLASS_DISPLAY, offset, &disp);
218 if (ret) {
219 debug("%s: device '%s' display not found (ret=%d)\n", __func__,
220 dev->name, ret);
221 return ret;
222 }
223
224 disp_uc_plat = dev_get_uclass_platdata(disp);
225 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
Simon Glass987a4042016-11-13 14:22:08 -0700226 if (display_in_use(disp)) {
227 debug(" - device in use\n");
228 return -EBUSY;
229 }
230
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700231 disp_uc_plat->source_id = remote_vop_id;
232 disp_uc_plat->src_dev = dev;
233
234 ret = device_probe(disp);
235 if (ret) {
236 debug("%s: device '%s' display won't probe (ret=%d)\n",
237 __func__, dev->name, ret);
238 return ret;
239 }
240
241 ret = display_read_timing(disp, &timing);
242 if (ret) {
243 debug("%s: Failed to read timings\n", __func__);
244 return ret;
245 }
246
Simon Glass9ed68262016-11-13 14:21:56 -0700247 ret = clk_get_by_index(dev, 1, &clk);
Stephen Warren135aa952016-06-17 09:44:00 -0600248 if (!ret)
249 ret = clk_set_rate(&clk, timing.pixelclock.typ);
Eric Gaoe07e5bd2017-05-02 18:23:51 +0800250 if (IS_ERR_VALUE(ret)) {
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700251 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
252 return ret;
253 }
254
Eric Gao8aed0d72017-05-02 18:23:53 +0800255 /* Set bitwidth for vop display according to vop mode */
256 switch (vop_id) {
257 case VOP_MODE_EDP:
258 case VOP_MODE_HDMI:
259 case VOP_MODE_LVDS:
260 l2bpp = VIDEO_BPP16;
261 break;
262 case VOP_MODE_MIPI:
263 l2bpp = VIDEO_BPP32;
264 break;
265 default:
266 l2bpp = VIDEO_BPP16;
267 }
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700268 rkvop_mode_set(regs, &timing, vop_id);
269
270 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
271
272 ret = display_enable(disp, 1 << l2bpp, &timing);
273 if (ret)
274 return ret;
275
276 uc_priv->xsize = timing.hactive.typ;
277 uc_priv->ysize = timing.vactive.typ;
278 uc_priv->bpix = l2bpp;
279 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
280
281 return 0;
282}
283
284static int rk_vop_probe(struct udevice *dev)
285{
286 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
287 const void *blob = gd->fdt_blob;
288 struct rk_vop_priv *priv = dev_get_priv(dev);
289 struct udevice *reg;
290 int ret, port, node;
291
292 /* Before relocation we don't need to do anything */
293 if (!(gd->flags & GD_FLG_RELOC))
294 return 0;
295
296 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
Simon Glassa821c4a2017-05-17 17:18:05 -0600297 priv->regs = (struct rk3288_vop *)devfdt_get_addr(dev);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700298
299 /* lcdc(vop) iodomain select 1.8V */
300 rk_setreg(&priv->grf->io_vsel, 1 << 0);
301
302 /*
303 * Try some common regulators. We should really get these from the
304 * device tree somehow.
305 */
306 ret = regulator_autoset_by_name("vcc18_lcd", &reg);
307 if (ret)
308 debug("%s: Cannot autoset regulator vcc18_lcd\n", __func__);
309 ret = regulator_autoset_by_name("VCC18_LCD", &reg);
310 if (ret)
311 debug("%s: Cannot autoset regulator VCC18_LCD\n", __func__);
312 ret = regulator_autoset_by_name("vdd10_lcd_pwren_h", &reg);
313 if (ret) {
314 debug("%s: Cannot autoset regulator vdd10_lcd_pwren_h\n",
315 __func__);
316 }
317 ret = regulator_autoset_by_name("vdd10_lcd", &reg);
318 if (ret) {
319 debug("%s: Cannot autoset regulator vdd10_lcd\n",
320 __func__);
321 }
322 ret = regulator_autoset_by_name("VDD10_LCD", &reg);
323 if (ret) {
324 debug("%s: Cannot autoset regulator VDD10_LCD\n",
325 __func__);
326 }
327 ret = regulator_autoset_by_name("vcc33_lcd", &reg);
328 if (ret)
329 debug("%s: Cannot autoset regulator vcc33_lcd\n", __func__);
330
331 /*
332 * Try all the ports until we find one that works. In practice this
333 * tries EDP first if available, then HDMI.
Simon Glass987a4042016-11-13 14:22:08 -0700334 *
335 * Note that rockchip_vop_set_clk() always uses NPLL as the source
336 * clock so it is currently not possible to use more than one display
337 * device simultaneously.
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700338 */
Simon Glasse160f7d2017-01-17 16:52:55 -0700339 port = fdt_subnode_offset(blob, dev_of_offset(dev), "port");
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700340 if (port < 0)
341 return -EINVAL;
342 for (node = fdt_first_subnode(blob, port);
343 node > 0;
344 node = fdt_next_subnode(blob, node)) {
Eric Gao8aed0d72017-05-02 18:23:53 +0800345 ret = rk_display_init(dev, plat->base, node);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700346 if (ret)
347 debug("Device failed: ret=%d\n", ret);
348 if (!ret)
349 break;
350 }
Simon Glassb55e04a2016-05-14 14:03:01 -0600351 video_set_flush_dcache(dev, 1);
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700352
353 return ret;
354}
355
356static int rk_vop_bind(struct udevice *dev)
357{
358 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
359
Eric Gaoc34bd8b2017-05-02 18:23:54 +0800360 plat->size = 1920 * 1200 * 4;
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700361
362 return 0;
363}
364
365static const struct video_ops rk_vop_ops = {
366};
367
368static const struct udevice_id rk_vop_ids[] = {
Eric Gao9f819932017-05-02 18:23:52 +0800369 { .compatible = "rockchip,rk3399-vop-big" },
370 { .compatible = "rockchip,rk3399-vop-lit" },
Simon Glass7b7ad5c2016-01-21 19:45:05 -0700371 { .compatible = "rockchip,rk3288-vop" },
372 { }
373};
374
375U_BOOT_DRIVER(rk_vop) = {
376 .name = "rk_vop",
377 .id = UCLASS_VIDEO,
378 .of_match = rk_vop_ids,
379 .ops = &rk_vop_ops,
380 .bind = rk_vop_bind,
381 .probe = rk_vop_probe,
382 .priv_auto_alloc_size = sizeof(struct rk_vop_priv),
383};