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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Thomas Abrahame39448e2016-04-23 22:18:13 +05302/*
3 * Configuration settings for the Espresso7420 board.
4 * Copyright (C) 2016 Samsung Electronics
5 * Thomas Abraham <thomas.ab@samsung.com>
Thomas Abrahame39448e2016-04-23 22:18:13 +05306 */
7
8#ifndef __CONFIG_EXYNOS7420_COMMON_H
9#define __CONFIG_EXYNOS7420_COMMON_H
10
Thomas Abrahame39448e2016-04-23 22:18:13 +053011#include <asm/arch/cpu.h> /* get chip and board defs */
12#include <linux/sizes.h>
13
Thomas Abrahame39448e2016-04-23 22:18:13 +053014/* Miscellaneous configurable options */
Thomas Abrahame39448e2016-04-23 22:18:13 +053015
Thomas Abrahame39448e2016-04-23 22:18:13 +053016/* select serial console configuration */
Thomas Abrahame39448e2016-04-23 22:18:13 +053017
Thomas Abraham95e74a32016-11-16 18:49:16 +053018#define CPU_RELEASE_ADDR secondary_boot_addr
Thomas Abrahame39448e2016-04-23 22:18:13 +053019
Thomas Abrahame39448e2016-04-23 22:18:13 +053020/* select serial console configuration */
Thomas Abrahame39448e2016-04-23 22:18:13 +053021
Tom Riniaa6e94d2022-11-16 13:10:37 -050022#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
Thomas Abrahame39448e2016-04-23 22:18:13 +053023#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
Tom Riniaa6e94d2022-11-16 13:10:37 -050024#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
Thomas Abrahame39448e2016-04-23 22:18:13 +053025#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
Tom Riniaa6e94d2022-11-16 13:10:37 -050026#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
Thomas Abrahame39448e2016-04-23 22:18:13 +053027#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
Tom Riniaa6e94d2022-11-16 13:10:37 -050028#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
Thomas Abrahame39448e2016-04-23 22:18:13 +053029#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
Tom Riniaa6e94d2022-11-16 13:10:37 -050030#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
Thomas Abrahame39448e2016-04-23 22:18:13 +053031#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
Tom Riniaa6e94d2022-11-16 13:10:37 -050032#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
Thomas Abrahame39448e2016-04-23 22:18:13 +053033#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
Tom Riniaa6e94d2022-11-16 13:10:37 -050034#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
Thomas Abrahame39448e2016-04-23 22:18:13 +053035#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
Tom Riniaa6e94d2022-11-16 13:10:37 -050036#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
Thomas Abrahame39448e2016-04-23 22:18:13 +053037#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
38
39/* Configuration of ENV Blocks */
Thomas Abrahame39448e2016-04-23 22:18:13 +053040
41#define BOOT_TARGET_DEVICES(func) \
42 func(MMC, mmc, 1) \
43 func(MMC, mmc, 0) \
44
45#ifndef MEM_LAYOUT_ENV_SETTINGS
46#define MEM_LAYOUT_ENV_SETTINGS \
47 "bootm_size=0x10000000\0" \
48 "kernel_addr_r=0x42000000\0" \
49 "fdt_addr_r=0x43000000\0" \
50 "ramdisk_addr_r=0x43300000\0" \
51 "scriptaddr=0x50000000\0" \
52 "pxefile_addr_r=0x51000000\0"
53#endif
54
55#ifndef EXYNOS_DEVICE_SETTINGS
56#define EXYNOS_DEVICE_SETTINGS \
57 "stdin=serial\0" \
58 "stdout=serial\0" \
59 "stderr=serial\0"
60#endif
61
62#ifndef EXYNOS_FDTFILE_SETTING
63#define EXYNOS_FDTFILE_SETTING
64#endif
65
Tom Rini0613c362022-12-04 10:03:50 -050066#define CFG_EXTRA_ENV_SETTINGS \
Thomas Abrahame39448e2016-04-23 22:18:13 +053067 EXYNOS_DEVICE_SETTINGS \
68 EXYNOS_FDTFILE_SETTING \
69 MEM_LAYOUT_ENV_SETTINGS
70
71#endif /* __CONFIG_EXYNOS7420_COMMON_H */