blob: 2034d0ebd9c8e0846f73c88772909ec80cd83da4 [file] [log] [blame]
Michal Simek6ded73a2016-09-19 10:41:55 +02001menu "FPGA support"
2
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05303config FPGA
4 bool
5
Patrick Bruenn98d62e62016-11-04 11:57:02 +01006config FPGA_ALTERA
7 bool "Enable Altera FPGA drivers"
8 select FPGA
9 help
10 Say Y here to enable the Altera FPGA driver
11
12 This provides basic infrastructure to support Altera FPGA devices.
13 Enable Altera FPGA specific functions which includes bitstream
14 (in BIT format), fpga and device validation.
15
Tien Fong Cheefa23ba12017-07-26 13:05:40 +080016config FPGA_SOCFPGA
17 bool "Enable Gen5 and Arria10 common FPGA drivers"
18 select FPGA_ALTERA
19 help
20 Say Y here to enable the Gen5 and Arria10 common FPGA driver
21
22 This provides common functionality for Gen5 and Arria10 devices.
23
Tom Rini6e52cb22022-06-12 20:02:00 -040024config FPGA_STRATIX_V
25 bool "Enable Stratix V FPGA drivers"
26 depends on FPGA_ALTERA
27 help
28 Say Y here to enable the Altera Stratix V FPGA specific driver.
29
Alexander Dahl312c4b12022-10-07 14:19:54 +020030config FPGA_ACEX1K
31 bool "Enable Altera ACEX 1K driver"
32 depends on FPGA_ALTERA
33 help
34 Say Y here to enable the Altera ACEX 1K FPGA specific driver.
35
Patrick Bruenn98d62e62016-11-04 11:57:02 +010036config FPGA_CYCLON2
37 bool "Enable Altera FPGA driver for Cyclone II"
38 depends on FPGA_ALTERA
39 help
40 Say Y here to enable the Altera Cyclone II FPGA specific driver
41
42 This provides common functionality for Altera Cyclone II devices.
43 Enable FPGA driver for loading bitstream in BIT and BIN format
44 on Altera Cyclone II device.
45
Chee Hong Angd2170162020-08-07 11:50:03 +080046config FPGA_INTEL_SDM_MAILBOX
47 bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
Siew Chin Lim9a5bbdf2021-03-01 20:04:10 +080048 depends on TARGET_SOCFPGA_SOC64
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080049 select FPGA_ALTERA
50 help
Chee Hong Angd2170162020-08-07 11:50:03 +080051 Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080052
Chee Hong Angd2170162020-08-07 11:50:03 +080053 This provides common functionality for Intel FPGA devices.
54 Enable FPGA driver for writing full bitstream into Intel FPGA
55 devices through SDM (Secure Device Manager) Mailbox.
Ang, Chee Hongc41e6602018-12-19 18:35:14 -080056
Simon Glass8badd332023-02-01 13:19:32 -070057config FPGA_LATTICE
58 bool "Enable Lattice FPGA driver"
59 help
60 This is used for the lattice FPGAs. Please check the source code as
61 there is no documentation for this at present.
62
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053063config FPGA_XILINX
64 bool "Enable Xilinx FPGA drivers"
65 select FPGA
66 help
67 Enable Xilinx FPGA specific functions which includes bitstream
68 (in BIT format), fpga and device validation.
69
70config FPGA_ZYNQMPPL
71 bool "Enable Xilinx FPGA driver for ZynqMP"
72 depends on FPGA_XILINX
73 help
74 Enable FPGA driver for loading bitstream in BIT and BIN format
75 on Xilinx Zynq UltraScale+ (ZynqMP) device.
76
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053077config FPGA_VERSALPL
78 bool "Enable Xilinx FPGA driver for Versal"
79 depends on FPGA_XILINX
80 help
81 Enable FPGA driver for loading bitstream in PDI format on Xilinx
82 Versal device. PDI is a new programmable device image format for
83 Versal. The bitstream will only be generated as PDI for Versal
84 platform.
85
Alexander Dahl312c4b12022-10-07 14:19:54 +020086config FPGA_SPARTAN2
87 bool "Enable Spartan2 FPGA driver"
88 depends on FPGA_XILINX
89 help
90 Enable Spartan2 FPGA driver.
91
Vipul Kumarf4158342018-02-16 18:02:49 +053092config FPGA_SPARTAN3
Michal Simeka225f812018-07-23 15:59:55 +020093 bool "Enable Spartan3 FPGA driver"
Robert Hancock25d63a32019-06-18 09:47:13 -060094 depends on FPGA_XILINX
Michal Simeka225f812018-07-23 15:59:55 +020095 help
96 Enable Spartan3 FPGA driver for loading in BIT format.
Vipul Kumarf4158342018-02-16 18:02:49 +053097
Robert Hancock25d63a32019-06-18 09:47:13 -060098config FPGA_VIRTEX2
99 bool "Enable Xilinx Virtex-II and later FPGA driver"
100 depends on FPGA_XILINX
101 help
102 Enable Virtex-II FPGA driver for loading in BIT format. This driver
103 also supports many newer Xilinx FPGA families.
104
Tom Rinif00f6762022-12-04 10:03:29 -0500105config SYS_FPGA_CHECK_BUSY
106 bool "Perform busy check during load from FPGA"
107 depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2
108
Vipul Kumar3990c9d2018-02-16 18:02:51 +0530109config FPGA_ZYNQPL
Michal Simeka225f812018-07-23 15:59:55 +0200110 bool "Enable Xilinx FPGA for Zynq"
111 depends on ARCH_ZYNQ
112 help
113 Enable FPGA driver for loading bitstream in BIT and BIN format
114 on Xilinx Zynq devices.
Vipul Kumar3990c9d2018-02-16 18:02:51 +0530115
Alexander Dahle8ffc1d2022-07-21 15:31:21 +0200116config SYS_FPGA_CHECK_CTRLC
117 bool "Allow Control-C to interrupt FPGA configuration"
118 depends on FPGA
119 help
120 User can interrupt FPGA configuration by pressing CTRL+C.
121
Alexander Dahl8c09cb62022-07-21 15:31:22 +0200122config SYS_FPGA_PROG_FEEDBACK
123 bool "Progress output during FPGA configuration"
124 depends on FPGA
125 default y if FPGA_VIRTEX2
126 help
127 Enable printing of hash marks during FPGA configuration.
128
Oleksandr Suvorovfb2b8852022-07-22 17:16:02 +0300129config FPGA_LOAD_SECURE
130 bool "Enable loading secure bitstreams"
131 depends on FPGA
132 help
133 Enables the fpga loads() functions that are used to load secure
134 (authenticated or encrypted or both) bitstreams on to FPGA.
135
136config SPL_FPGA_LOAD_SECURE
137 bool "Enable loading secure bitstreams for SPL"
138 depends on SPL_FPGA
139 help
140 Enables the fpga loads() functions that are used to load secure
141 (authenticated or encrypted or both) bitstreams on to FPGA.
142
Alexander Dahl1323d082022-09-30 14:04:30 +0200143config DM_FPGA
144 bool "Enable Driver Model for FPGA drivers"
145 depends on DM
146 select FPGA
147 help
148 Enable driver model for Field-Programmable Gate Array (FPGA) devices.
149 The devices cover a wide range of applications and are configured at
150 runtime by loading a bitstream into the FPGA device.
151 Loading a bitstream from any kind of storage is the main task of the
152 FPGA drivers.
153 For now this uclass has no methods yet.
154
155config SANDBOX_FPGA
156 bool "Enable sandbox FPGA driver"
157 depends on SANDBOX && DM_FPGA
158 help
159 This is a driver model based FPGA driver for sandbox.
160 Currently it is a stub only, as there are no usable uclass methods yet.
161
Tom Rini8fe042b2023-01-10 11:19:37 -0500162config MAX_FPGA_DEVICES
163 int "Maximum number of FPGA devices"
164 depends on FPGA
165 default 5
166
Michal Simek6ded73a2016-09-19 10:41:55 +0200167endmenu