blob: 725abe9e1f9c35c838431c7e2ce371c5e79c4b2b [file] [log] [blame]
wdenk37bd3212002-11-03 11:21:28 +00001/*
2 * (C) Copyright 2000
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include "cpciiser4.h"
26#include <asm/processor.h>
27#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000028
29/*cmd_boot.c*/
30
31extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
32
wdenk37bd3212002-11-03 11:21:28 +000033
34/* ------------------------------------------------------------------------- */
35
36#if 0
37#define FPGA_DEBUG
38#endif
39
40#if 0
41#define FPGA_DEBUG2
42#endif
43
44/* fpga configuration data - generated by bin2cc */
45const unsigned char fpgadata[] = {
46#include "fpgadata.c"
47};
48
49/*
50 * include common fpga code (for esd boards)
51 */
52#include "../common/fpga.c"
53
54
55int board_pre_init (void)
56{
57 DECLARE_GLOBAL_DATA_PTR;
58
59 int index, len, i;
60 volatile unsigned char dummy;
61 int status;
62
63#ifdef FPGA_DEBUG
64 /* set up serial port with default baudrate */
65 (void) get_clocks ();
66 gd->baudrate = CONFIG_BAUDRATE;
67 serial_init ();
68 console_init_f ();
69#endif
70
71 /*
72 * Boot onboard FPGA
73 */
74 status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
75 if (status != 0) {
76 /* booting FPGA failed */
77#ifndef FPGA_DEBUG
78 /* set up serial port with default baudrate */
79 (void) get_clocks ();
80 gd->baudrate = CONFIG_BAUDRATE;
81 serial_init ();
82 console_init_f ();
83#endif
84 printf ("\nFPGA: Booting failed ");
85 switch (status) {
86 case ERROR_FPGA_PRG_INIT_LOW:
87 printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
88 break;
89 case ERROR_FPGA_PRG_INIT_HIGH:
90 printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
91 break;
92 case ERROR_FPGA_PRG_DONE:
93 printf ("(Timeout: DONE not high after programming FPGA)\n ");
94 break;
95 }
96
97 /* display infos on fpgaimage */
98 index = 15;
99 for (i = 0; i < 4; i++) {
100 len = fpgadata[index];
101 printf ("FPGA: %s\n", &(fpgadata[index + 1]));
102 index += len + 3;
103 }
104 putc ('\n');
105 /* delayed reboot */
106 for (i = 20; i > 0; i--) {
107 printf ("Rebooting in %2d seconds \r", i);
108 for (index = 0; index < 1000; index++)
109 udelay (1000);
110 }
111 putc ('\n');
112 do_reset (NULL, 0, 0, NULL);
113 }
114
115 /*
116 * Init FPGA via RESET (read access on CS3)
117 */
118 dummy = *(unsigned char *) 0xf0200000;
119
120 /*
121 * IRQ 0-15 405GP internally generated; active high; level sensitive
122 * IRQ 16 405GP internally generated; active low; level sensitive
123 * IRQ 17-24 RESERVED
124 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
125 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
126 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
127 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
128 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
129 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
130 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
131 */
132 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
133 mtdcr (uicer, 0x00000000); /* disable all ints */
134 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
135 /* mtdcr(uicpr, 0xFFFFFF81); / set int polarities */
136 mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
137 mtdcr (uictr, 0x10000000); /* set int trigger levels */
138 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
139 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
140
141 return 0;
142}
143
144
145/* ------------------------------------------------------------------------- */
146
147/*
148 * Check Board Identity:
149 */
150
151int checkboard (void)
152{
153 int index;
154 int len;
155 unsigned char str[64];
156 int i = getenv_r ("serial#", str, sizeof (str));
157
158 puts ("Board: ");
159
160 if (!i || strncmp (str, "CPCIISER4", 9)) {
161 puts ("### No HW ID - assuming CPCIISER4\n");
162 return (0);
163 }
164
165 puts (str);
166
167 puts ("\nFPGA: ");
168
169 /* display infos on fpgaimage */
170 index = 15;
171 for (i = 0; i < 4; i++) {
172 len = fpgadata[index];
173 printf ("%s ", &(fpgadata[index + 1]));
174 index += len + 3;
175 }
176
177 putc ('\n');
178
179 return 0;
180}
181
182/* ------------------------------------------------------------------------- */
183
184long int initdram (int board_type)
185{
186 return (16 * 1024 * 1024);
187}
188
189/* ------------------------------------------------------------------------- */
190
191int testdram (void)
192{
193 /* TODO: XXX XXX XXX */
194 printf ("test: 16 MB - ok\n");
195
196 return (0);
197}
198
199/* ------------------------------------------------------------------------- */