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Vikas Manocha6a12ceb2016-02-11 15:47:19 -08001/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02002 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
Vikas Manochafd03b832017-02-12 10:25:46 -08009#include <clk.h>
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080010#include <dm.h>
11#include <asm/io.h>
12#include <serial.h>
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090013#include <asm/arch/stm32.h>
Patrice Chotardae74de02018-01-12 09:23:49 +010014#include "serial_stm32.h"
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080015
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080016static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
17{
Patrice Chotard60a996b2017-09-27 15:44:50 +020018 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
19 bool stm32f4 = plat->uart_info->stm32f4;
20 fdt_addr_t base = plat->base;
Patrice Chotard27265ce2017-07-18 09:29:08 +020021 u32 int_div, mantissa, fraction, oversampling;
Toshifumi NISHINAGAba0a3c12016-07-08 01:02:24 +090022
Patrice Chotard27265ce2017-07-18 09:29:08 +020023 int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020024
25 if (int_div < 16) {
26 oversampling = 8;
Patrice Chotard60a996b2017-09-27 15:44:50 +020027 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020028 } else {
29 oversampling = 16;
Patrice Chotard60a996b2017-09-27 15:44:50 +020030 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020031 }
32
33 mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
34 fraction = int_div % oversampling;
35
Patrice Chotard60a996b2017-09-27 15:44:50 +020036 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080037
38 return 0;
39}
40
41static int stm32_serial_getc(struct udevice *dev)
42{
Patrice Chotard60a996b2017-09-27 15:44:50 +020043 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
44 bool stm32f4 = plat->uart_info->stm32f4;
45 fdt_addr_t base = plat->base;
Patrice Chotard7b3b74d2018-04-20 08:59:06 +020046 u32 isr = readl(base + ISR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080047
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020048 if ((isr & USART_ISR_FLAG_RXNE) == 0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080049 return -EAGAIN;
50
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020051 if (isr & USART_ISR_FLAG_ORE) {
Patrice Chotard7b3b74d2018-04-20 08:59:06 +020052 if (!stm32f4)
53 setbits_le32(base + ICR_OFFSET, USART_ICR_OREF);
54 else
55 readl(base + RDR_OFFSET(stm32f4));
56 return -EIO;
57 }
58
Patrice Chotard60a996b2017-09-27 15:44:50 +020059 return readl(base + RDR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080060}
61
62static int stm32_serial_putc(struct udevice *dev, const char c)
63{
Patrice Chotard60a996b2017-09-27 15:44:50 +020064 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
65 bool stm32f4 = plat->uart_info->stm32f4;
66 fdt_addr_t base = plat->base;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080067
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020068 if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_FLAG_TXE) == 0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080069 return -EAGAIN;
70
Patrice Chotard60a996b2017-09-27 15:44:50 +020071 writel(c, base + TDR_OFFSET(stm32f4));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080072
73 return 0;
74}
75
76static int stm32_serial_pending(struct udevice *dev, bool input)
77{
Patrice Chotard60a996b2017-09-27 15:44:50 +020078 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
79 bool stm32f4 = plat->uart_info->stm32f4;
80 fdt_addr_t base = plat->base;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080081
82 if (input)
Patrice Chotard60a996b2017-09-27 15:44:50 +020083 return readl(base + ISR_OFFSET(stm32f4)) &
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020084 USART_ISR_FLAG_RXNE ? 1 : 0;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080085 else
Patrice Chotard60a996b2017-09-27 15:44:50 +020086 return readl(base + ISR_OFFSET(stm32f4)) &
Patrice Chotard8dc4e1f2018-04-20 08:59:07 +020087 USART_ISR_FLAG_TXE ? 0 : 1;
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080088}
89
90static int stm32_serial_probe(struct udevice *dev)
91{
Patrice Chotard60a996b2017-09-27 15:44:50 +020092 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
Patrice Chotard9a212d72017-09-27 15:44:53 +020093 struct clk clk;
Patrice Chotard60a996b2017-09-27 15:44:50 +020094 fdt_addr_t base = plat->base;
Patrice Chotard9a212d72017-09-27 15:44:53 +020095 int ret;
Patrice Chotard60a996b2017-09-27 15:44:50 +020096 bool stm32f4;
97 u8 uart_enable_bit;
98
99 plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
100 stm32f4 = plat->uart_info->stm32f4;
101 uart_enable_bit = plat->uart_info->uart_enable_bit;
Vikas Manochafd03b832017-02-12 10:25:46 -0800102
Vikas Manochafd03b832017-02-12 10:25:46 -0800103 ret = clk_get_by_index(dev, 0, &clk);
104 if (ret < 0)
105 return ret;
106
107 ret = clk_enable(&clk);
108 if (ret) {
109 dev_err(dev, "failed to enable clock\n");
110 return ret;
111 }
Vikas Manochafd03b832017-02-12 10:25:46 -0800112
Patrice Chotard27265ce2017-07-18 09:29:08 +0200113 plat->clock_rate = clk_get_rate(&clk);
114 if (plat->clock_rate < 0) {
115 clk_disable(&clk);
116 return plat->clock_rate;
117 };
118
Patrice Chotard7b3b74d2018-04-20 08:59:06 +0200119 /* Disable uart-> enable fifo-> enable uart */
Patrice Chotard60a996b2017-09-27 15:44:50 +0200120 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
121 BIT(uart_enable_bit));
Patrice Chotard2a7ecc52017-09-27 15:44:51 +0200122 if (plat->uart_info->has_fifo)
123 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
Patrice Chotard60a996b2017-09-27 15:44:50 +0200124 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
125 BIT(uart_enable_bit));
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800126
127 return 0;
128}
129
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800130static const struct udevice_id stm32_serial_id[] = {
Patrice Chotard6c30f152017-09-27 15:44:52 +0200131 { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
Patrice Chotard2a7ecc52017-09-27 15:44:51 +0200132 { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
133 { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800134 {}
135};
136
137static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
138{
139 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800140
Patrice Chotard60a996b2017-09-27 15:44:50 +0200141 plat->base = devfdt_get_addr(dev);
142 if (plat->base == FDT_ADDR_T_NONE)
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800143 return -EINVAL;
144
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800145 return 0;
146}
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800147
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800148static const struct dm_serial_ops stm32_serial_ops = {
149 .putc = stm32_serial_putc,
150 .pending = stm32_serial_pending,
151 .getc = stm32_serial_getc,
152 .setbrg = stm32_serial_setbrg,
153};
154
155U_BOOT_DRIVER(serial_stm32) = {
Patrice Chotardae74de02018-01-12 09:23:49 +0100156 .name = "serial_stm32",
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800157 .id = UCLASS_SERIAL,
Vikas Manocha42bf5e72017-02-12 10:25:44 -0800158 .of_match = of_match_ptr(stm32_serial_id),
159 .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
160 .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
Vikas Manocha6a12ceb2016-02-11 15:47:19 -0800161 .ops = &stm32_serial_ops,
162 .probe = stm32_serial_probe,
163 .flags = DM_FLAG_PRE_RELOC,
164};