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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tom Warren9112ef82011-11-05 09:48:11 +00002/*
Allen Martin6b3a03e2013-03-16 18:58:06 +00003 * Copyright (c) 2010-2013 NVIDIA Corporation
Tom Warren9112ef82011-11-05 09:48:11 +00004 * With help from the mpc8xxx SPI driver
5 * With more help from omap3_spi SPI driver
Tom Warren9112ef82011-11-05 09:48:11 +00006 */
7
8#include <common.h>
Simon Glassfda6fac2014-10-13 23:42:13 -06009#include <dm.h>
10#include <errno.h>
Simon Glass10453152019-11-14 12:57:30 -070011#include <time.h>
Tom Warren9112ef82011-11-05 09:48:11 +000012#include <asm/io.h>
13#include <asm/gpio.h>
Tom Warren9112ef82011-11-05 09:48:11 +000014#include <asm/arch/clock.h>
15#include <asm/arch/pinmux.h>
Tom Warren150c2492012-09-19 15:50:56 -070016#include <asm/arch-tegra/clk_rst.h>
Tom Warren150c2492012-09-19 15:50:56 -070017#include <spi.h>
Allen Martin8f1b46b2013-01-29 13:51:24 +000018#include <fdtdec.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060019#include "tegra_spi.h"
Allen Martin8f1b46b2013-01-29 13:51:24 +000020
21DECLARE_GLOBAL_DATA_PTR;
Tom Warren9112ef82011-11-05 09:48:11 +000022
Jagan Tekif6922482015-10-23 01:39:06 +053023#define SPI_CMD_GO BIT(30)
Allen Martin7a49ba62013-03-16 18:58:05 +000024#define SPI_CMD_ACTIVE_SCLK_SHIFT 26
25#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
Jagan Tekif6922482015-10-23 01:39:06 +053026#define SPI_CMD_CK_SDA BIT(21)
Allen Martin7a49ba62013-03-16 18:58:05 +000027#define SPI_CMD_ACTIVE_SDA_SHIFT 18
28#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
Jagan Tekif6922482015-10-23 01:39:06 +053029#define SPI_CMD_CS_POL BIT(16)
30#define SPI_CMD_TXEN BIT(15)
31#define SPI_CMD_RXEN BIT(14)
32#define SPI_CMD_CS_VAL BIT(13)
33#define SPI_CMD_CS_SOFT BIT(12)
34#define SPI_CMD_CS_DELAY BIT(9)
35#define SPI_CMD_CS3_EN BIT(8)
36#define SPI_CMD_CS2_EN BIT(7)
37#define SPI_CMD_CS1_EN BIT(6)
38#define SPI_CMD_CS0_EN BIT(5)
39#define SPI_CMD_BIT_LENGTH BIT(4)
Jagan Teki76538ec2015-10-23 01:03:10 +053040#define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
Allen Martin7a49ba62013-03-16 18:58:05 +000041
Jagan Tekif6922482015-10-23 01:39:06 +053042#define SPI_STAT_BSY BIT(31)
43#define SPI_STAT_RDY BIT(30)
44#define SPI_STAT_RXF_FLUSH BIT(29)
45#define SPI_STAT_TXF_FLUSH BIT(28)
46#define SPI_STAT_RXF_UNR BIT(27)
47#define SPI_STAT_TXF_OVF BIT(26)
48#define SPI_STAT_RXF_EMPTY BIT(25)
49#define SPI_STAT_RXF_FULL BIT(24)
50#define SPI_STAT_TXF_EMPTY BIT(23)
51#define SPI_STAT_TXF_FULL BIT(22)
52#define SPI_STAT_SEL_TXRX_N BIT(16)
53#define SPI_STAT_CUR_BLKCNT BIT(15)
Allen Martin7a49ba62013-03-16 18:58:05 +000054
55#define SPI_TIMEOUT 1000
56#define TEGRA_SPI_MAX_FREQ 52000000
57
58struct spi_regs {
59 u32 command; /* SPI_COMMAND_0 register */
60 u32 status; /* SPI_STATUS_0 register */
61 u32 rx_cmp; /* SPI_RX_CMP_0 register */
62 u32 dma_ctl; /* SPI_DMA_CTL_0 register */
63 u32 tx_fifo; /* SPI_TX_FIFO_0 register */
64 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
65 u32 rx_fifo; /* SPI_RX_FIFO_0 register */
66};
67
Simon Glassfda6fac2014-10-13 23:42:13 -060068struct tegra20_sflash_priv {
Allen Martin7a49ba62013-03-16 18:58:05 +000069 struct spi_regs *regs;
Tom Warren9112ef82011-11-05 09:48:11 +000070 unsigned int freq;
71 unsigned int mode;
Allen Martin8f1b46b2013-01-29 13:51:24 +000072 int periph_id;
Allen Martin6b3a03e2013-03-16 18:58:06 +000073 int valid;
Simon Glassfda6fac2014-10-13 23:42:13 -060074 int last_transaction_us;
Tom Warren9112ef82011-11-05 09:48:11 +000075};
76
Simon Glassfda6fac2014-10-13 23:42:13 -060077int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
78 struct spi_cs_info *info)
Tom Warren9112ef82011-11-05 09:48:11 +000079{
Allen Martin00a27492012-08-31 08:30:00 +000080 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
Simon Glassfda6fac2014-10-13 23:42:13 -060081 if (cs != 0)
Bin Meng4b060002019-09-09 06:00:01 -070082 return -EINVAL;
Tom Warren9112ef82011-11-05 09:48:11 +000083 else
Simon Glassfda6fac2014-10-13 23:42:13 -060084 return 0;
Tom Warren9112ef82011-11-05 09:48:11 +000085}
86
Simon Glassfda6fac2014-10-13 23:42:13 -060087static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
Tom Warren9112ef82011-11-05 09:48:11 +000088{
Simon Glassfda6fac2014-10-13 23:42:13 -060089 struct tegra_spi_platdata *plat = bus->platdata;
90 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -070091 int node = dev_of_offset(bus);
Tom Warren9112ef82011-11-05 09:48:11 +000092
Simon Glassa821c4a2017-05-17 17:18:05 -060093 plat->base = devfdt_get_addr(bus);
Simon Glass000f15f2017-07-25 08:30:00 -060094 plat->periph_id = clock_decode_periph_id(bus);
Simon Glassfda6fac2014-10-13 23:42:13 -060095
96 if (plat->periph_id == PERIPH_ID_NONE) {
97 debug("%s: could not decode periph id %d\n", __func__,
98 plat->periph_id);
99 return -FDT_ERR_NOTFOUND;
Tom Warren9112ef82011-11-05 09:48:11 +0000100 }
101
Simon Glassfda6fac2014-10-13 23:42:13 -0600102 /* Use 500KHz as a suitable default */
103 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
104 500000);
105 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
106 "spi-deactivate-delay", 0);
107 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
108 __func__, plat->base, plat->periph_id, plat->frequency,
109 plat->deactivate_delay_us);
Tom Warren9112ef82011-11-05 09:48:11 +0000110
Simon Glassfda6fac2014-10-13 23:42:13 -0600111 return 0;
Tom Warren9112ef82011-11-05 09:48:11 +0000112}
113
Simon Glassfda6fac2014-10-13 23:42:13 -0600114static int tegra20_sflash_probe(struct udevice *bus)
Tom Warren9112ef82011-11-05 09:48:11 +0000115{
Simon Glassfda6fac2014-10-13 23:42:13 -0600116 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
117 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
Tom Warren9112ef82011-11-05 09:48:11 +0000118
Simon Glassfda6fac2014-10-13 23:42:13 -0600119 priv->regs = (struct spi_regs *)plat->base;
120
121 priv->last_transaction_us = timer_get_us();
122 priv->freq = plat->frequency;
123 priv->periph_id = plat->periph_id;
124
Stephen Warren4832c7f2016-08-18 10:53:33 -0600125 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
126 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
127 priv->freq);
128
Simon Glassfda6fac2014-10-13 23:42:13 -0600129 return 0;
Tom Warren9112ef82011-11-05 09:48:11 +0000130}
131
Simon Glass9694b722015-04-19 09:05:40 -0600132static int tegra20_sflash_claim_bus(struct udevice *dev)
Tom Warren9112ef82011-11-05 09:48:11 +0000133{
Simon Glass9694b722015-04-19 09:05:40 -0600134 struct udevice *bus = dev->parent;
Simon Glassfda6fac2014-10-13 23:42:13 -0600135 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
136 struct spi_regs *regs = priv->regs;
Tom Warren9112ef82011-11-05 09:48:11 +0000137 u32 reg;
138
139 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
Simon Glassfda6fac2014-10-13 23:42:13 -0600140 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
141 priv->freq);
Tom Warren9112ef82011-11-05 09:48:11 +0000142
143 /* Clear stale status here */
144 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
145 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
146 writel(reg, &regs->status);
Allen Martin78f47b72013-03-16 18:58:07 +0000147 debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
Tom Warren9112ef82011-11-05 09:48:11 +0000148
149 /*
150 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
151 */
Simon Glassfda6fac2014-10-13 23:42:13 -0600152 reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
153 if (priv->mode & 2)
Tom Warren9112ef82011-11-05 09:48:11 +0000154 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
155 clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
156 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
Allen Martin78f47b72013-03-16 18:58:07 +0000157 debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
Tom Warren9112ef82011-11-05 09:48:11 +0000158
159 /*
Allen Martin00a27492012-08-31 08:30:00 +0000160 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
Tom Warren9112ef82011-11-05 09:48:11 +0000161 * issue.
162 */
Stephen Warren70ad3752014-03-21 12:28:58 -0600163 pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
164 pinmux_tristate_disable(PMUX_PINGRP_LSPI);
165 pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
Simon Glass4560c7d2011-11-05 04:46:50 +0000166
Tom Warren9112ef82011-11-05 09:48:11 +0000167 return 0;
168}
169
Simon Glassfda6fac2014-10-13 23:42:13 -0600170static void spi_cs_activate(struct udevice *dev)
Tom Warren9112ef82011-11-05 09:48:11 +0000171{
Simon Glassfda6fac2014-10-13 23:42:13 -0600172 struct udevice *bus = dev->parent;
173 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
174 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
175
176 /* If it's too soon to do another transaction, wait */
177 if (pdata->deactivate_delay_us &&
178 priv->last_transaction_us) {
179 ulong delay_us; /* The delay completed so far */
180 delay_us = timer_get_us() - priv->last_transaction_us;
181 if (delay_us < pdata->deactivate_delay_us)
182 udelay(pdata->deactivate_delay_us - delay_us);
183 }
Tom Warren9112ef82011-11-05 09:48:11 +0000184
Tom Warren9112ef82011-11-05 09:48:11 +0000185 /* CS is negated on Tegra, so drive a 1 to get a 0 */
Simon Glassfda6fac2014-10-13 23:42:13 -0600186 setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
Tom Warren9112ef82011-11-05 09:48:11 +0000187}
188
Simon Glassfda6fac2014-10-13 23:42:13 -0600189static void spi_cs_deactivate(struct udevice *dev)
Tom Warren9112ef82011-11-05 09:48:11 +0000190{
Simon Glassfda6fac2014-10-13 23:42:13 -0600191 struct udevice *bus = dev->parent;
192 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
193 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
Tom Warren9112ef82011-11-05 09:48:11 +0000194
195 /* CS is negated on Tegra, so drive a 0 to get a 1 */
Simon Glassfda6fac2014-10-13 23:42:13 -0600196 clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
197
198 /* Remember time of this transaction so we can honour the bus delay */
199 if (pdata->deactivate_delay_us)
200 priv->last_transaction_us = timer_get_us();
Tom Warren9112ef82011-11-05 09:48:11 +0000201}
202
Simon Glassfda6fac2014-10-13 23:42:13 -0600203static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
204 const void *data_out, void *data_in,
205 unsigned long flags)
Tom Warren9112ef82011-11-05 09:48:11 +0000206{
Simon Glassfda6fac2014-10-13 23:42:13 -0600207 struct udevice *bus = dev->parent;
208 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
209 struct spi_regs *regs = priv->regs;
Tom Warren9112ef82011-11-05 09:48:11 +0000210 u32 reg, tmpdout, tmpdin = 0;
211 const u8 *dout = data_out;
212 u8 *din = data_in;
213 int num_bytes;
214 int ret;
215
Simon Glassfda6fac2014-10-13 23:42:13 -0600216 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
217 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
Tom Warren9112ef82011-11-05 09:48:11 +0000218 if (bitlen % 8)
219 return -1;
220 num_bytes = bitlen / 8;
221
222 ret = 0;
223
224 reg = readl(&regs->status);
225 writel(reg, &regs->status); /* Clear all SPI events via R/W */
226 debug("spi_xfer entry: STATUS = %08x\n", reg);
227
228 reg = readl(&regs->command);
229 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
230 writel(reg, &regs->command);
231 debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
232
233 if (flags & SPI_XFER_BEGIN)
Simon Glassfda6fac2014-10-13 23:42:13 -0600234 spi_cs_activate(dev);
Tom Warren9112ef82011-11-05 09:48:11 +0000235
236 /* handle data in 32-bit chunks */
237 while (num_bytes > 0) {
238 int bytes;
239 int is_read = 0;
240 int tm, i;
241
242 tmpdout = 0;
243 bytes = (num_bytes > 4) ? 4 : num_bytes;
244
245 if (dout != NULL) {
246 for (i = 0; i < bytes; ++i)
247 tmpdout = (tmpdout << 8) | dout[i];
248 }
249
250 num_bytes -= bytes;
251 if (dout)
252 dout += bytes;
253
254 clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
255 bytes * 8 - 1);
256 writel(tmpdout, &regs->tx_fifo);
257 setbits_le32(&regs->command, SPI_CMD_GO);
258
259 /*
260 * Wait for SPI transmit FIFO to empty, or to time out.
261 * The RX FIFO status will be read and cleared last
262 */
263 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
264 u32 status;
265
266 status = readl(&regs->status);
267
268 /* We can exit when we've had both RX and TX activity */
269 if (is_read && (status & SPI_STAT_TXF_EMPTY))
270 break;
271
272 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
273 SPI_STAT_RDY)
274 tm++;
275
276 else if (!(status & SPI_STAT_RXF_EMPTY)) {
277 tmpdin = readl(&regs->rx_fifo);
278 is_read = 1;
279
280 /* swap bytes read in */
281 if (din != NULL) {
282 for (i = bytes - 1; i >= 0; --i) {
283 din[i] = tmpdin & 0xff;
284 tmpdin >>= 8;
285 }
286 din += bytes;
287 }
288 }
289 }
290
291 if (tm >= SPI_TIMEOUT)
292 ret = tm;
293
294 /* clear ACK RDY, etc. bits */
295 writel(readl(&regs->status), &regs->status);
296 }
297
298 if (flags & SPI_XFER_END)
Simon Glassfda6fac2014-10-13 23:42:13 -0600299 spi_cs_deactivate(dev);
Tom Warren9112ef82011-11-05 09:48:11 +0000300
301 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
302 tmpdin, readl(&regs->status));
303
304 if (ret) {
305 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
306 return -1;
307 }
308
309 return 0;
310}
Simon Glassfda6fac2014-10-13 23:42:13 -0600311
312static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
313{
314 struct tegra_spi_platdata *plat = bus->platdata;
315 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
316
317 if (speed > plat->frequency)
318 speed = plat->frequency;
319 priv->freq = speed;
320 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
321
322 return 0;
323}
324
325static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
326{
327 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
328
329 priv->mode = mode;
330 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
331
332 return 0;
333}
334
335static const struct dm_spi_ops tegra20_sflash_ops = {
336 .claim_bus = tegra20_sflash_claim_bus,
337 .xfer = tegra20_sflash_xfer,
338 .set_speed = tegra20_sflash_set_speed,
339 .set_mode = tegra20_sflash_set_mode,
340 .cs_info = tegra20_sflash_cs_info,
341};
342
343static const struct udevice_id tegra20_sflash_ids[] = {
344 { .compatible = "nvidia,tegra20-sflash" },
345 { }
346};
347
348U_BOOT_DRIVER(tegra20_sflash) = {
349 .name = "tegra20_sflash",
350 .id = UCLASS_SPI,
351 .of_match = tegra20_sflash_ids,
352 .ops = &tegra20_sflash_ops,
353 .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
354 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
355 .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
Simon Glassfda6fac2014-10-13 23:42:13 -0600356 .probe = tegra20_sflash_probe,
357};