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Sergei Poselenovb4489622007-07-05 08:17:37 +02001/*
2 * (C) Copyright 2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Author: Igor Lisitsin <igor@emcraft.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovb4489622007-07-05 08:17:37 +02008 */
9
10#include <common.h>
11
12/*
13 * Ethernet test
14 *
15 * The Ethernet Media Access Controllers (EMAC) are tested in the
16 * internal loopback mode.
17 * The controllers are configured accordingly and several packets
18 * are transmitted. The configurable test parameters are:
19 * MIN_PACKET_LENGTH - minimum size of packet to transmit
20 * MAX_PACKET_LENGTH - maximum size of packet to transmit
Stefan Roeseac692432010-11-26 19:17:40 +010021 * CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
22 * is tested with a different frame length. Starting with
23 * MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
24 * Defaults to 10 and can be overriden in the board config header.
Sergei Poselenovb4489622007-07-05 08:17:37 +020025 */
26
Sergei Poselenovb4489622007-07-05 08:17:37 +020027#include <post.h>
28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#if CONFIG_POST & CONFIG_SYS_POST_ETHER
Sergei Poselenovb4489622007-07-05 08:17:37 +020030
31#include <asm/cache.h>
32#include <asm/io.h>
33#include <asm/processor.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020034#include <asm/ppc4xx-mal.h>
35#include <asm/ppc4xx-emac.h>
Sergei Poselenovb4489622007-07-05 08:17:37 +020036#include <malloc.h>
37
38DECLARE_GLOBAL_DATA_PTR;
39
Stefan Roese7d47cee2007-10-25 12:24:59 +020040/*
41 * Get count of EMAC devices (doesn't have to be the max. possible number
42 * supported by the cpu)
43 *
44 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
45 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
46 * 405EX/405EXr eval board, using the same binary.
47 */
48#if defined(CONFIG_BOARD_EMAC_COUNT)
49#define LAST_EMAC_NUM board_emac_count()
50#else /* CONFIG_BOARD_EMAC_COUNT */
51#if defined(CONFIG_HAS_ETH3)
52#define LAST_EMAC_NUM 4
53#elif defined(CONFIG_HAS_ETH2)
54#define LAST_EMAC_NUM 3
55#elif defined(CONFIG_HAS_ETH1)
56#define LAST_EMAC_NUM 2
57#else
58#define LAST_EMAC_NUM 1
59#endif
60#endif /* CONFIG_BOARD_EMAC_COUNT */
61
Sergei Poselenovb4489622007-07-05 08:17:37 +020062#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
63#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
64#endif
65
66#define MIN_PACKET_LENGTH 64
Stefan Roeseac692432010-11-26 19:17:40 +010067#define MAX_PACKET_LENGTH 1514
68#ifndef CONFIG_SYS_POST_ETH_LOOPS
69#define CONFIG_SYS_POST_ETH_LOOPS 10
70#endif
71#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
72 CONFIG_SYS_POST_ETH_LOOPS)
Sergei Poselenovb4489622007-07-05 08:17:37 +020073
74static volatile mal_desc_t tx __cacheline_aligned;
75static volatile mal_desc_t rx __cacheline_aligned;
76static char *tx_buf;
77static char *rx_buf;
78
Stefan Roese7d47cee2007-10-25 12:24:59 +020079int board_emac_count(void);
80
Sergei Poselenovb4489622007-07-05 08:17:37 +020081static void ether_post_init (int devnum, int hw_addr)
82{
83 int i;
Sergei Poselenovb4489622007-07-05 08:17:37 +020084#if defined(CONFIG_440GX) || \
85 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
86 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roesec5a172a2007-08-14 14:41:55 +020087 unsigned mode_reg;
Sergei Poselenovb4489622007-07-05 08:17:37 +020088 sys_info_t sysinfo;
89#endif
90#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
91 unsigned long mfr;
92#endif
93
94#if defined(CONFIG_440GX) || \
95 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
96 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
97 /* Need to get the OPB frequency so we can access the PHY */
98 get_sys_info (&sysinfo);
99#endif
100
101#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
102 /* provide clocks for EMAC internal loopback */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200103 mfsdr (SDR0_MFR, mfr);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200104 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200105 mtsdr (SDR0_MFR, mfr);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200106 sync ();
107#endif
108 /* reset emac */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200109 out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200110 sync ();
111
112 for (i = 0;; i++) {
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200113 if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
Sergei Poselenovb4489622007-07-05 08:17:37 +0200114 break;
115 if (i >= 1000) {
116 printf ("Timeout resetting EMAC\n");
117 break;
118 }
119 udelay (1000);
120 }
121#if defined(CONFIG_440GX) || \
122 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
123 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
124 /* Whack the M1 register */
125 mode_reg = 0x0;
126 if (sysinfo.freqOPB <= 50000000);
127 else if (sysinfo.freqOPB <= 66666667)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200128 mode_reg |= EMAC_MR1_OBCI_66;
Sergei Poselenovb4489622007-07-05 08:17:37 +0200129 else if (sysinfo.freqOPB <= 83333333)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200130 mode_reg |= EMAC_MR1_OBCI_83;
Sergei Poselenovb4489622007-07-05 08:17:37 +0200131 else if (sysinfo.freqOPB <= 100000000)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200132 mode_reg |= EMAC_MR1_OBCI_100;
Sergei Poselenovb4489622007-07-05 08:17:37 +0200133 else
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200134 mode_reg |= EMAC_MR1_OBCI_GT100;
Sergei Poselenovb4489622007-07-05 08:17:37 +0200135
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200136 out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200137
138#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
139
140 /* set the Mal configuration reg */
141#if defined(CONFIG_440GX) || \
142 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
143 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200144 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
Sergei Poselenovb4489622007-07-05 08:17:37 +0200145 MAL_CR_PLBLT_DEFAULT | 0x00330000);
146#else
Stefan Roesed1c3b272009-09-09 16:25:29 +0200147 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200148 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
149 if (get_pvr() == PVR_440GP_RB) {
Stefan Roesed1c3b272009-09-09 16:25:29 +0200150 mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200151 }
152#endif
153 /* setup buffer descriptors */
154 tx.ctrl = MAL_TX_CTRL_WRAP;
155 tx.data_len = 0;
156 tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
157
158 rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
159 rx.data_len = 0;
160 rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
Stefan Roesef71b2882007-10-31 20:47:26 +0100161 flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
162 flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200163
164 switch (devnum) {
165 case 1:
166 /* setup MAL tx & rx channel pointers */
167#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200168 mtdcr (MAL0_TXCTP2R, &tx);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200169#else
Stefan Roesed1c3b272009-09-09 16:25:29 +0200170 mtdcr (MAL0_TXCTP1R, &tx);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200171#endif
172#if defined(CONFIG_440)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200173 mtdcr (MAL0_TXBADDR, 0x0);
174 mtdcr (MAL0_RXBADDR, 0x0);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200175#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200176 mtdcr (MAL0_RXCTP1R, &rx);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200177 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200178 mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200179 break;
180 case 0:
181 default:
182 /* setup MAL tx & rx channel pointers */
183#if defined(CONFIG_440)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200184 mtdcr (MAL0_TXBADDR, 0x0);
185 mtdcr (MAL0_RXBADDR, 0x0);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200186#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200187 mtdcr (MAL0_TXCTP0R, &tx);
188 mtdcr (MAL0_RXCTP0R, &rx);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200189 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200190 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200191 break;
192 }
193
194 /* Enable MAL transmit and receive channels */
195#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200196 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2)));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200197#else
Stefan Roesed1c3b272009-09-09 16:25:29 +0200198 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200199#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200200 mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200201
202 /* set internal loopback mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200204 out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
205 EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
206 EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
207 in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
Stefan Roesec5a172a2007-08-14 14:41:55 +0200208#else
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200209 out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
210 EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
211 EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
212 in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
Stefan Roesec5a172a2007-08-14 14:41:55 +0200213#endif
Sergei Poselenovb4489622007-07-05 08:17:37 +0200214
215 /* set transmit enable & receive enable */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200216 out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200217
218 /* enable broadcast address */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200219 out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200220
221 /* set transmit request threshold register */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200222 out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
Sergei Poselenovb4489622007-07-05 08:17:37 +0200223
224 /* set receive low/high water mark register */
225#if defined(CONFIG_440)
226 /* 440s has a 64 byte burst length */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200227 out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200228#else
229 /* 405s have a 16 byte burst length */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200230 out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200231#endif /* defined(CONFIG_440) */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200232 out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200233
234 /* Set fifo limit entry in tx mode 0 */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200235 out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200236 /* Frame gap set */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200237 out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200238 sync ();
239}
240
241static void ether_post_halt (int devnum, int hw_addr)
242{
243 int i = 0;
244#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
245 unsigned long mfr;
246#endif
247
248 /* 1st reset MAL channel */
249 /* Note: writing a 0 to a channel has no effect */
250#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200251 mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200252#else
Stefan Roesed1c3b272009-09-09 16:25:29 +0200253 mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200254#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200255 mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200256
257 /* wait for reset */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200258 while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) {
Sergei Poselenovb4489622007-07-05 08:17:37 +0200259 if (i++ >= 1000)
260 break;
261 udelay (1000);
262 }
263 /* emac reset */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200264 out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200265
266#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
267 /* remove clocks for EMAC internal loopback */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200268 mfsdr (SDR0_MFR, mfr);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200269 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200270 mtsdr (SDR0_MFR, mfr);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200271#endif
272}
273
274static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
275{
276 int i = 0;
277
278 while (tx.ctrl & MAL_TX_CTRL_READY) {
279 if (i++ > 100) {
280 printf ("TX timeout\n");
281 return;
282 }
283 udelay (1000);
Stefan Roesef71b2882007-10-31 20:47:26 +0100284 invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200285 }
286 tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
287 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
288 tx.data_len = length;
289 memcpy (tx.data_ptr, packet, length);
Stefan Roesef71b2882007-10-31 20:47:26 +0100290 flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
291 flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200292 sync ();
293
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200294 out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200295 sync ();
296}
297
298static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
299{
300 int length;
301 int i = 0;
302
303 while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
304 if (i++ > 100) {
305 printf ("RX timeout\n");
306 return 0;
307 }
308 udelay (1000);
Stefan Roesef71b2882007-10-31 20:47:26 +0100309 invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200310 }
311 length = rx.data_len - 4;
Stefan Roesef71b2882007-10-31 20:47:26 +0100312 if (length <= max_length) {
313 invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200314 memcpy(packet, rx.data_ptr, length);
Stefan Roesef71b2882007-10-31 20:47:26 +0100315 }
Sergei Poselenovb4489622007-07-05 08:17:37 +0200316 sync ();
317
318 rx.ctrl |= MAL_RX_CTRL_EMPTY;
Stefan Roesef71b2882007-10-31 20:47:26 +0100319 flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200320 sync ();
321
322 return length;
323}
324
325 /*
326 * Test routines
327 */
328
329static void packet_fill (char *packet, int length)
330{
331 char c = (char) length;
332 int i;
333
334 /* set up ethernet header */
335 memset (packet, 0xff, 14);
336
337 for (i = 14; i < length; i++) {
338 packet[i] = c++;
339 }
340}
341
342static int packet_check (char *packet, int length)
343{
344 char c = (char) length;
345 int i;
346
347 for (i = 14; i < length; i++) {
348 if (packet[i] != c++)
349 return -1;
350 }
351
352 return 0;
353}
354
Stefan Roeseac692432010-11-26 19:17:40 +0100355 char packet_send[MAX_PACKET_LENGTH];
356 char packet_recv[MAX_PACKET_LENGTH];
Sergei Poselenovb4489622007-07-05 08:17:37 +0200357static int test_ctlr (int devnum, int hw_addr)
358{
359 int res = -1;
Sergei Poselenovb4489622007-07-05 08:17:37 +0200360 int length;
Sergei Poselenovb4489622007-07-05 08:17:37 +0200361 int l;
362
363 ether_post_init (devnum, hw_addr);
364
Stefan Roeseac692432010-11-26 19:17:40 +0100365 for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
366 l -= PACKET_INCR) {
367 packet_fill (packet_send, l);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200368
Stefan Roeseac692432010-11-26 19:17:40 +0100369 ether_post_send (devnum, hw_addr, packet_send, l);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200370
Stefan Roeseac692432010-11-26 19:17:40 +0100371 length = ether_post_recv (devnum, hw_addr, packet_recv,
372 sizeof (packet_recv));
Sergei Poselenovb4489622007-07-05 08:17:37 +0200373
Stefan Roeseac692432010-11-26 19:17:40 +0100374 if (length != l || packet_check (packet_recv, length) < 0) {
375 goto Done;
Sergei Poselenovb4489622007-07-05 08:17:37 +0200376 }
377 }
378
379 res = 0;
380
381Done:
382
383 ether_post_halt (devnum, hw_addr);
384
385 if (res != 0) {
386 post_log ("EMAC%d test failed\n", devnum);
387 }
388
389 return res;
390}
391
392int ether_post_test (int flags)
393{
394 int res = 0;
Stefan Roese7d47cee2007-10-25 12:24:59 +0200395 int i;
Sergei Poselenovb4489622007-07-05 08:17:37 +0200396
397 /* Allocate tx & rx packet buffers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398 tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
399 rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
Sergei Poselenovb4489622007-07-05 08:17:37 +0200400
401 if (!tx_buf || !rx_buf) {
402 printf ("Failed to allocate packet buffers\n");
403 res = -1;
404 goto out_free;
405 }
406
Stefan Roese7d47cee2007-10-25 12:24:59 +0200407 for (i = 0; i < LAST_EMAC_NUM; i++) {
408 if (test_ctlr (i, i*0x100))
409 res = -1;
410 }
Sergei Poselenovb4489622007-07-05 08:17:37 +0200411
412out_free:
413 free (tx_buf);
414 free (rx_buf);
415
416 return res;
417}
418
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */