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Shengzhou Liu48c6f322014-11-24 17:11:56 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +08004 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 *
Shengzhou Liu48c6f322014-11-24 17:11:56 +08006 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <command.h>
11#include <netdev.h>
12#include <asm/mmu.h>
13#include <asm/processor.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_law.h>
16#include <asm/fsl_serdes.h>
17#include <asm/fsl_portals.h>
18#include <asm/fsl_liodn.h>
19#include <malloc.h>
20#include <fm_eth.h>
21#include <fsl_mdio.h>
22#include <miiphy.h>
23#include <phy.h>
Shaohui Xie8225b2f2015-10-26 19:47:47 +080024#include <fsl_dtsec.h>
Shengzhou Liu48c6f322014-11-24 17:11:56 +080025#include <asm/fsl_serdes.h>
Shengzhou Liue26416a2014-12-17 16:51:08 +080026#include "../common/fman.h"
Shengzhou Liu48c6f322014-11-24 17:11:56 +080027
28int board_eth_init(bd_t *bis)
29{
30#if defined(CONFIG_FMAN_ENET)
31 int i, interface;
32 struct memac_mdio_info dtsec_mdio_info;
33 struct memac_mdio_info tgec_mdio_info;
34 struct mii_dev *dev;
35 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
36 u32 srds_s1;
37
38 srds_s1 = in_be32(&gur->rcwsr[4]) &
39 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
40 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
41
42 dtsec_mdio_info.regs =
43 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
44
45 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
46
47 /* Register the 1G MDIO bus */
48 fm_memac_mdio_init(bis, &dtsec_mdio_info);
49
50 tgec_mdio_info.regs =
51 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
52 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
53
54 /* Register the 10G MDIO bus */
55 fm_memac_mdio_init(bis, &tgec_mdio_info);
56
Shengzhou Liue26416a2014-12-17 16:51:08 +080057 /* Set the on-board RGMII PHY address */
Shengzhou Liu48c6f322014-11-24 17:11:56 +080058 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
59
60 switch (srds_s1) {
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080061#ifdef CONFIG_T1024RDB
Shengzhou Liu48c6f322014-11-24 17:11:56 +080062 case 0x95:
Shengzhou Liue26416a2014-12-17 16:51:08 +080063 /* set the on-board RGMII2 PHY */
64 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
65
66 /* set 10G XFI with Aquantia AQR105 PHY */
Shengzhou Liu48c6f322014-11-24 17:11:56 +080067 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
68 break;
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080069#endif
70 case 0x6a:
71 case 0x6b:
Shengzhou Liue26416a2014-12-17 16:51:08 +080072 case 0x77:
73 case 0x135:
74 /* set the on-board 2.5G SGMII AQR105 PHY */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080075 fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
76#ifdef CONFIG_T1023RDB
77 /* set the on-board 1G SGMII RTL8211F PHY */
78 fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
79#endif
Shengzhou Liue26416a2014-12-17 16:51:08 +080080 break;
Shengzhou Liu48c6f322014-11-24 17:11:56 +080081 default:
82 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
83 srds_s1);
84 break;
85 }
86
87 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
88 interface = fm_info_get_enet_if(i);
89 switch (interface) {
90 case PHY_INTERFACE_MODE_RGMII:
91 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
92 fm_info_set_mdio(i, dev);
93 break;
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080094 case PHY_INTERFACE_MODE_SGMII:
95#if defined(CONFIG_T1023RDB)
96 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
97#elif defined(CONFIG_T1024RDB)
98 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
99#endif
100 fm_info_set_mdio(i, dev);
101 break;
Shengzhou Liue26416a2014-12-17 16:51:08 +0800102 case PHY_INTERFACE_MODE_SGMII_2500:
103 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
104 fm_info_set_mdio(i, dev);
105 break;
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800106 default:
107 break;
108 }
109 }
110
111 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
112 switch (fm_info_get_enet_if(i)) {
113 case PHY_INTERFACE_MODE_XGMII:
114 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
115 fm_info_set_mdio(i, dev);
116 break;
117 default:
118 break;
119 }
120 }
121
122 cpu_eth_init(bis);
123#endif /* CONFIG_FMAN_ENET */
124
125 return pci_eth_init(bis);
126}
127
Shengzhou Liue26416a2014-12-17 16:51:08 +0800128void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
129 enum fm_port port, int offset)
130{
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800131#if defined(CONFIG_T1024RDB)
132 if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
133 (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
134 (port == FM1_DTSEC3)) {
Shengzhou Liue26416a2014-12-17 16:51:08 +0800135 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
Shengzhou Liuea753262015-04-14 17:56:50 +0800136 fdt_setprop_string(fdt, offset, "phy-connection-type",
137 "sgmii-2500");
Shengzhou Liue26416a2014-12-17 16:51:08 +0800138 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
139 }
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800140#endif
Shengzhou Liue26416a2014-12-17 16:51:08 +0800141}
142
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800143void fdt_fixup_board_enet(void *fdt)
144{
145}