blob: 3b1efca3730ebdac6fd82c889e138a81978e3fd6 [file] [log] [blame]
Vikas Manocha0a836ce2015-05-03 14:10:34 -07001/dts-v1/;
2
3/ {
4 model = "ST STV0991 application board";
5 compatible = "st,stv0991";
6 #address-cells = <1>;
7 #size-cells = <1>;
8
9 chosen {
10 stdout-path = &uart0;
11 };
12
13 memory {
14 device_type="memory";
15 reg = <0x0 0x198000>;
16 };
17
18 uart0: serial@0x80406000 {
19 compatible = "arm,pl011", "arm,primecell";
20 reg = <0x80406000 0x1000>;
21 clock = <2700000>;
22 };
Vikas Manocha51d55832015-07-02 18:29:42 -070023
24 aliases {
25 spi0 = "/spi@80203000"; /* QSPI */
26 };
27
28 qspi: spi@80203000 {
29 compatible = "cadence,qspi";
30 #address-cells = <1>;
31 #size-cells = <0>;
32 reg = <0x80203000 0x100>,
33 <0x40000000 0x1000000>;
34 clocks = <3750000>;
35 ext-decoder = <0>; /* external decoder */
36 num-cs = <4>;
37 fifo-depth = <256>;
38 bus-num = <0>;
39 status = "okay";
40
41 flash0: n25q32@0 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 compatible = "spi-flash";
45 reg = <0>; /* chip select */
46 spi-max-frequency = <50000000>;
47 m25p,fast-read;
48 page-size = <256>;
49 block-size = <16>; /* 2^16, 64KB */
50 read-delay = <4>; /* delay value in read data capture register */
51 tshsl-ns = <50>;
52 tsd2d-ns = <50>;
53 tchsh-ns = <4>;
54 tslch-ns = <4>;
55 };
56 };
Vikas Manocha0a836ce2015-05-03 14:10:34 -070057};