blob: 1f733d112dd7719fbb0c23b09ac1a2c3ff86902d [file] [log] [blame]
Weijie Gao4bc01042022-05-20 11:22:21 +08001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2022 MediaTek Inc. All rights reserved.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7621_H
9#define __CONFIG_MT7621_H
10
Weijie Gao4bc01042022-05-20 11:22:21 +080011#define CONFIG_SYS_SDRAM_BASE 0x80000000
12
13#define CONFIG_VERY_BIG_RAM
14#define CONFIG_MAX_MEM_MAPPED 0x1c000000
15
16#define CONFIG_SYS_INIT_SP_OFFSET 0x800000
17
Weijie Gao4bc01042022-05-20 11:22:21 +080018/* MMC */
19#define MMC_SUPPORTS_TUNING
20
21/* NAND */
Weijie Gao4bc01042022-05-20 11:22:21 +080022
23/* Serial SPL */
24#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Weijie Gao4bc01042022-05-20 11:22:21 +080025#define CONFIG_SYS_NS16550_CLK 50000000
Weijie Gao4bc01042022-05-20 11:22:21 +080026#define CONFIG_SYS_NS16550_COM1 0xbe000c00
27#endif
28
29/* Serial common */
30#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
31 230400, 460800, 921600 }
32
33/* Dummy value */
34#define CONFIG_SYS_UBOOT_BASE 0
35
36#endif /* __CONFIG_MT7621_H */