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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 921bb8641d15f8a2570d43321e5c74ff65aa28f3 / . / arch / arm / mach-davinci / Kconfig
blob: adc50922c8f562d9572f2cc0b78cd5ba596c28de [file] [log] [blame]
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]1if ARCH_DAVINCI
2
3choice
4 prompt "DaVinci board select"
Joe Hershbergera26cd042015-05-12 14:46:23 -0500[diff] [blame]5 optional
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]6
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]7config TARGET_DA850EVM
8 bool "DA850 EVM board"
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]9 select MACH_DAVINCI_DA850_EVM
10 select SOC_DA850
Masahiro Yamada02627352014-10-20 17:45:56 +0900[diff] [blame]11 select SUPPORT_SPL
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]12
Simon Glass67619462015-08-30 19:18:59 -0600[diff] [blame]13config TARGET_OMAPL138_LCDK
14 bool "OMAPL138 LCDK"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]15 select SOC_DA8XX
Simon Glass67619462015-08-30 19:18:59 -0600[diff] [blame]16 select SUPPORT_SPL
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]17
David Lechner2ac07f72016-02-26 00:46:07 -0600[diff] [blame]18config TARGET_LEGOEV3
19 bool "LEGO MINDSTORMS EV3"
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]20 select MACH_DAVINCI_DA850_EVM
21 select SOC_DA850
David Lechner2ac07f72016-02-26 00:46:07 -0600[diff] [blame]22
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]23endchoice
24
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]25config SYS_SOC
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]26 default "davinci"
27
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]28config DA850_LOWLEVEL
29 bool "Enable Lowlevel DA850 initialization"
30 depends on SOC_DA850
31
Fabien Parentf519b362016-11-29 14:23:36 +0100[diff] [blame]32config SYS_DA850_PLL_INIT
33 bool
34
Fabien Parentb31bf372016-11-29 14:23:37 +0100[diff] [blame]35config SYS_DA850_DDR_INIT
36 bool
37
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]38config SOC_DA850
39 bool
40 select SOC_DA8XX
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]41
42config SOC_DA8XX
43 bool
Lokesh Vutla891ab742018-03-16 14:22:12 +0530[diff] [blame]44 select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
Michal Simek58008cb2018-07-23 15:55:15 +0200[diff] [blame]45 select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]46
47config MACH_DAVINCI_DA850_EVM
48 bool
49
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]50if SYS_DA850_PLL_INIT
51comment "DA850 PLL Initialization Parameters"
52
53config SYS_DV_CLKMODE
54 int "PLLCTL Clock Mode"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]55 default 0
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]56 help
57 Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
58
59config SYS_DA850_PLL0_POSTDIV
60 int "PLLC0 PLL Post-Divider"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]61 default 1
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]62 help
63 Value written to PLLC0 PLL Post-Divider Control Register
64
65config SYS_DA850_PLL0_PLLDIV1
66 hex "PLLC0 Divider 1"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]67 default 0x8000
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]68 help
69 Value written to PLLC0 Divider 1 register
70
71config SYS_DA850_PLL0_PLLDIV2
72 hex "PLLC0 Divider 2"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]73 default 0x8001
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]74 help
75 Value written to PLLC0 Divider 2 register
76
77config SYS_DA850_PLL0_PLLDIV3
78 hex "PLLC0 Divider 3"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]79 default 0x8002
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]80 help
81 Value written to PLLC0 Divider 3 register
82
83config SYS_DA850_PLL0_PLLDIV4
84 hex "PLLC0 Divider 4"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]85 default 0x8003
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]86 help
87 Value written to PLLC0 Divider 4 register
88
89config SYS_DA850_PLL0_PLLDIV5
90 hex "PLLC0 Divider 5"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]91 default 0x8002
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]92 help
93 Value written to PLLC0 Divider 5 register
94
95config SYS_DA850_PLL0_PLLDIV6
96 hex "PLLC0 Divider 6"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]97 default 0x8000
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]98 help
99 Value written to PLLC0 Divider 6 register
100
101config SYS_DA850_PLL0_PLLDIV7
102 hex "PLLC0 Divider 7"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]103 default 0x8005
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]104 help
105 Value written to PLLC0 Divider 7 register
106
107config SYS_DA850_PLL1_POSTDIV
108 hex "PLLC1 PLL Post-Divider"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]109 default 1
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]110 help
111 Value written to PLLC1 PLL Post-Divider Control Register
112
113config SYS_DA850_PLL1_PLLDIV1
114 hex "PLLC1 Divider 2"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]115 default 0x8000
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]116 help
117 Value written to PLLC1 Divider 1 register
118
119config SYS_DA850_PLL1_PLLDIV2
120 hex "PLLC1 Divider 2"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]121 default 0x8001
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]122 help
123 Value written to PLLC1 Divider 2 register
124
125config SYS_DA850_PLL1_PLLDIV3
126 hex "PLLC1 Divider 3"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame]127 default 0x8002
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]128 help
129 Value written to PLLC1 Divider 3 register
130
131endif
132
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]133source "board/davinci/da8xxevm/Kconfig"
David Lechner2ac07f72016-02-26 00:46:07 -0600[diff] [blame]134source "board/lego/ev3/Kconfig"
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]135
Philipp Tomsichb5299932017-08-03 23:23:55 +0200[diff] [blame]136config SPL_LDSCRIPT
Philipp Tomsichb5299932017-08-03 23:23:55 +0200[diff] [blame]137 default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
138
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]139endif