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Jagan Teki337fcdc2018-12-31 15:35:01 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun50i-h6-ccu.h>
13#include <dt-bindings/reset/sun50i-h6-ccu.h>
Simon Glasscd93d622020-05-10 11:40:13 -060014#include <linux/bitops.h>
Jagan Teki337fcdc2018-12-31 15:35:01 +053015
16static struct ccu_clk_gate h6_gates[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +000017 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
18 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
19 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
Jagan Teki337fcdc2018-12-31 15:35:01 +053020 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
21 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
23 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
Jagan Teki82111462019-02-27 20:02:06 +053024
25 [CLK_SPI0] = GATE(0x940, BIT(31)),
26 [CLK_SPI1] = GATE(0x944, BIT(31)),
27
28 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
29 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
Jagan Teki68620c92019-02-28 00:26:57 +053030
31 [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
Andre Przywara106c1302019-06-23 15:09:48 +010032
33 [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
34 [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
35
36 [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
37
38 [CLK_USB_HSIC] = GATE(0xa7c, BIT(26)),
39 [CLK_USB_HSIC_12M] = GATE(0xa7c, BIT(27)),
40 [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
41 [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
42
43 [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
44 [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
45 [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
Samuel Hollandfa7eabf2021-02-07 23:57:20 -060046 [CLK_BUS_XHCI] = GATE(0xa8c, BIT(5)),
Andre Przywara106c1302019-06-23 15:09:48 +010047 [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
48 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
Jagan Teki337fcdc2018-12-31 15:35:01 +053049};
50
51static struct ccu_reset h6_resets[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +000052 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
53 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
54 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
Jagan Teki337fcdc2018-12-31 15:35:01 +053055 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
56 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
57 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
58 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
Jagan Teki82111462019-02-27 20:02:06 +053059
60 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
61 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
Jagan Teki68620c92019-02-28 00:26:57 +053062
63 [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
Andre Przywara106c1302019-06-23 15:09:48 +010064
65 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
66
67 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
68
69 [RST_USB_HSIC] = RESET(0xa7c, BIT(28)),
70 [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
71
72 [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
73 [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
74 [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
Samuel Hollandfa7eabf2021-02-07 23:57:20 -060075 [RST_BUS_XHCI] = RESET(0xa8c, BIT(21)),
Andre Przywara106c1302019-06-23 15:09:48 +010076 [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
77 [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
Jagan Teki337fcdc2018-12-31 15:35:01 +053078};
79
80static const struct ccu_desc h6_ccu_desc = {
81 .gates = h6_gates,
82 .resets = h6_resets,
83};
84
85static int h6_clk_bind(struct udevice *dev)
86{
87 return sunxi_reset_bind(dev, ARRAY_SIZE(h6_resets));
88}
89
90static const struct udevice_id h6_ccu_ids[] = {
91 { .compatible = "allwinner,sun50i-h6-ccu",
92 .data = (ulong)&h6_ccu_desc },
93 { }
94};
95
96U_BOOT_DRIVER(clk_sun50i_h6) = {
97 .name = "sun50i_h6_ccu",
98 .id = UCLASS_CLK,
99 .of_match = h6_ccu_ids,
Simon Glass41575d82020-12-03 16:55:17 -0700100 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki337fcdc2018-12-31 15:35:01 +0530101 .ops = &sunxi_clk_ops,
102 .probe = sunxi_clk_probe,
103 .bind = h6_clk_bind,
104};