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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm64 / freescale / imx8mp-verdin.dtsi
blob: c3305f0d40010041a89b855a5f19b8f2d62a521f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7#include <dt-bindings/pwm/pwm.h>
8#include "imx8mp.dtsi"
9
10/ {
11 chosen {
12 stdout-path = &uart3;
13 };
14
15 aliases {
16 /* Ethernet aliases to ensure correct MAC addresses */
17 ethernet0 = &eqos;
18 ethernet1 = &fec;
19 rtc0 = &rtc_i2c;
20 rtc1 = &snvs_rtc;
21 };
22
23 backlight: backlight {
24 compatible = "pwm-backlight";
25 brightness-levels = <0 45 63 88 119 158 203 255>;
26 default-brightness-level = <4>;
27 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
28 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
31 power-supply = <&reg_3p3v>;
32 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
34 status = "disabled";
35 };
36
37 backlight_mezzanine: backlight-mezzanine {
38 compatible = "pwm-backlight";
39 brightness-levels = <0 45 63 88 119 158 203 255>;
40 default-brightness-level = <4>;
41 /* Verdin GPIO 4 (SODIMM 212) */
42 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
43 /* Verdin PWM_2 (SODIMM 16) */
44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
45 status = "disabled";
46 };
47
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame^]48 connector {
49 compatible = "gpio-usb-b-connector", "usb-b-connector";
50 id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
51 label = "Type-C";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_usb_1_id>;
54 self-powered;
55 type = "micro";
56 vbus-supply = <&reg_usb1_vbus>;
57
58 port {
59 usb_dr_connector: endpoint {
60 remote-endpoint = <&usb3_dwc>;
61 };
62 };
63 };
64
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]65 gpio-keys {
66 compatible = "gpio-keys";
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_gpio_keys>;
69
70 key-wakeup {
71 debounce-interval = <10>;
72 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
73 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
74 label = "Wake-Up";
75 linux,code = <KEY_WAKEUP>;
76 wakeup-source;
77 };
78 };
79
80 /* Carrier Board Supplies */
81 reg_1p8v: regulator-1p8v {
82 compatible = "regulator-fixed";
83 regulator-max-microvolt = <1800000>;
84 regulator-min-microvolt = <1800000>;
85 regulator-name = "+V1.8_SW";
86 };
87
88 reg_3p3v: regulator-3p3v {
89 compatible = "regulator-fixed";
90 regulator-max-microvolt = <3300000>;
91 regulator-min-microvolt = <3300000>;
92 regulator-name = "+V3.3_SW";
93 };
94
95 reg_5p0v: regulator-5p0v {
96 compatible = "regulator-fixed";
97 regulator-max-microvolt = <5000000>;
98 regulator-min-microvolt = <5000000>;
99 regulator-name = "+V5_SW";
100 };
101
102 /* Non PMIC On-module Supplies */
103 reg_module_eth1phy: regulator-module-eth1phy {
104 compatible = "regulator-fixed";
105 enable-active-high;
106 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
107 off-on-delay-us = <500000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_eth>;
110 regulator-always-on;
111 regulator-boot-on;
112 regulator-max-microvolt = <3300000>;
113 regulator-min-microvolt = <3300000>;
114 regulator-name = "On-module +V3.3_ETH";
115 startup-delay-us = <200000>;
116 vin-supply = <&reg_vdd_3v3>;
117 };
118
119 reg_usb1_vbus: regulator-usb1-vbus {
120 compatible = "regulator-fixed";
121 enable-active-high;
122 /* Verdin USB_1_EN (SODIMM 155) */
123 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_usb1_vbus>;
126 regulator-max-microvolt = <5000000>;
127 regulator-min-microvolt = <5000000>;
128 regulator-name = "USB_1_EN";
129 };
130
131 reg_usb2_vbus: regulator-usb2-vbus {
132 compatible = "regulator-fixed";
133 enable-active-high;
134 /* Verdin USB_2_EN (SODIMM 185) */
135 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_usb2_vbus>;
138 regulator-max-microvolt = <5000000>;
139 regulator-min-microvolt = <5000000>;
140 regulator-name = "USB_2_EN";
141 };
142
143 reg_usdhc2_vmmc: regulator-usdhc2 {
144 compatible = "regulator-fixed";
145 enable-active-high;
146 /* Verdin SD_1_PWR_EN (SODIMM 76) */
147 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
148 off-on-delay-us = <100000>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
151 regulator-max-microvolt = <3300000>;
152 regulator-min-microvolt = <3300000>;
153 regulator-name = "+V3.3_SD";
154 startup-delay-us = <2000>;
155 };
156
157 reserved-memory {
158 #address-cells = <2>;
159 #size-cells = <2>;
160 ranges;
161
162 /* Use the kernel configuration settings instead */
163 /delete-node/ linux,cma;
164 };
165};
166
167&A53_0 {
168 cpu-supply = <&reg_vdd_arm>;
169};
170
171&A53_1 {
172 cpu-supply = <&reg_vdd_arm>;
173};
174
175&A53_2 {
176 cpu-supply = <&reg_vdd_arm>;
177};
178
179&A53_3 {
180 cpu-supply = <&reg_vdd_arm>;
181};
182
183&cpu_alert0 {
184 temperature = <95000>;
185};
186
187&cpu_crit0 {
188 temperature = <105000>;
189};
190
191/* Verdin SPI_1 */
192&ecspi1 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_ecspi1>;
198};
199
200/* Verdin ETH_1 (On-module PHY) */
201&eqos {
202 phy-handle = <&ethphy0>;
203 phy-mode = "rgmii-id";
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_eqos>;
206 snps,force_thresh_dma_mode;
207 snps,mtl-rx-config = <&mtl_rx_setup>;
208 snps,mtl-tx-config = <&mtl_tx_setup>;
209
210 mdio {
211 compatible = "snps,dwmac-mdio";
212 #address-cells = <1>;
213 #size-cells = <0>;
214
215 ethphy0: ethernet-phy@7 {
216 compatible = "ethernet-phy-ieee802.3-c22";
217 eee-broken-100tx;
218 eee-broken-1000t;
219 interrupt-parent = <&gpio1>;
220 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
221 micrel,led-mode = <0>;
222 reg = <7>;
223 };
224 };
225
226 mtl_rx_setup: rx-queues-config {
227 snps,rx-queues-to-use = <5>;
228 snps,rx-sched-sp;
229
230 queue0 {
231 snps,dcb-algorithm;
232 snps,priority = <0x1>;
233 snps,map-to-dma-channel = <0>;
234 };
235
236 queue1 {
237 snps,dcb-algorithm;
238 snps,priority = <0x2>;
239 snps,map-to-dma-channel = <1>;
240 };
241
242 queue2 {
243 snps,dcb-algorithm;
244 snps,priority = <0x4>;
245 snps,map-to-dma-channel = <2>;
246 };
247
248 queue3 {
249 snps,dcb-algorithm;
250 snps,priority = <0x8>;
251 snps,map-to-dma-channel = <3>;
252 };
253
254 queue4 {
255 snps,dcb-algorithm;
256 snps,priority = <0xf0>;
257 snps,map-to-dma-channel = <4>;
258 };
259 };
260
261 mtl_tx_setup: tx-queues-config {
262 snps,tx-queues-to-use = <5>;
263 snps,tx-sched-sp;
264
265 queue0 {
266 snps,dcb-algorithm;
267 snps,priority = <0x1>;
268 };
269
270 queue1 {
271 snps,dcb-algorithm;
272 snps,priority = <0x2>;
273 };
274
275 queue2 {
276 snps,dcb-algorithm;
277 snps,priority = <0x4>;
278 };
279
280 queue3 {
281 snps,dcb-algorithm;
282 snps,priority = <0x8>;
283 };
284
285 queue4 {
286 snps,dcb-algorithm;
287 snps,priority = <0xf0>;
288 };
289 };
290};
291
292/* Verdin ETH_2_RGMII */
293&fec {
294 fsl,magic-packet;
295 phy-handle = <&ethphy1>;
296 phy-mode = "rgmii-id";
297 pinctrl-names = "default", "sleep";
298 pinctrl-0 = <&pinctrl_fec>;
299 pinctrl-1 = <&pinctrl_fec_sleep>;
300
301 mdio {
302 #address-cells = <1>;
303 #size-cells = <0>;
304
305 ethphy1: ethernet-phy@7 {
306 compatible = "ethernet-phy-ieee802.3-c22";
307 interrupt-parent = <&gpio4>;
308 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
309 micrel,led-mode = <0>;
310 reg = <7>;
311 };
312 };
313};
314
315/* Verdin CAN_1 */
316&flexcan1 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_flexcan1>;
319 status = "disabled";
320};
321
322/* Verdin CAN_2 */
323&flexcan2 {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_flexcan2>;
326 status = "disabled";
327};
328
329/* Verdin QSPI_1 */
330&flexspi {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_flexspi0>;
333};
334
335&gpio1 {
336 gpio-line-names = "SODIMM_206",
337 "SODIMM_208",
338 "",
339 "",
340 "",
341 "SODIMM_210",
342 "SODIMM_212",
343 "SODIMM_216",
344 "SODIMM_218",
345 "",
346 "",
347 "SODIMM_16",
348 "SODIMM_155",
349 "SODIMM_157",
350 "SODIMM_185",
351 "SODIMM_91";
352};
353
354&gpio2 {
355 gpio-line-names = "",
356 "",
357 "",
358 "",
359 "",
360 "",
361 "SODIMM_143",
362 "SODIMM_141",
363 "",
364 "",
365 "SODIMM_161",
366 "",
367 "SODIMM_84",
368 "SODIMM_78",
369 "SODIMM_74",
370 "SODIMM_80",
371 "SODIMM_82",
372 "SODIMM_70",
373 "SODIMM_72";
374};
375
376&gpio3 {
377 gpio-line-names = "SODIMM_52",
378 "SODIMM_54",
379 "",
380 "",
381 "",
382 "",
383 "SODIMM_56",
384 "SODIMM_58",
385 "SODIMM_60",
386 "SODIMM_62",
387 "",
388 "",
389 "",
390 "",
391 "SODIMM_66",
392 "",
393 "SODIMM_64",
394 "",
395 "",
396 "SODIMM_34",
397 "SODIMM_19",
398 "",
399 "SODIMM_32",
400 "",
401 "",
402 "SODIMM_30",
403 "SODIMM_59",
404 "SODIMM_57",
405 "SODIMM_63",
406 "SODIMM_61";
407};
408
409&gpio4 {
410 gpio-line-names = "SODIMM_252",
411 "SODIMM_222",
412 "SODIMM_36",
413 "SODIMM_220",
414 "SODIMM_193",
415 "SODIMM_191",
416 "SODIMM_201",
417 "SODIMM_203",
418 "SODIMM_205",
419 "SODIMM_207",
420 "SODIMM_199",
421 "SODIMM_197",
422 "SODIMM_221",
423 "SODIMM_219",
424 "SODIMM_217",
425 "SODIMM_215",
426 "SODIMM_211",
427 "SODIMM_213",
428 "SODIMM_189",
429 "SODIMM_244",
430 "SODIMM_38",
431 "",
432 "SODIMM_76",
433 "SODIMM_135",
434 "SODIMM_133",
435 "SODIMM_17",
436 "SODIMM_24",
437 "SODIMM_26",
438 "SODIMM_21",
439 "SODIMM_256",
440 "SODIMM_48",
441 "SODIMM_44";
442
443 ctrl-sleep-moci-hog {
444 gpio-hog;
445 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
446 gpios = <29 GPIO_ACTIVE_HIGH>;
447 line-name = "CTRL_SLEEP_MOCI#";
448 output-high;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
451 };
452};
453
454/* On-module I2C */
455&i2c1 {
456 clock-frequency = <400000>;
457 pinctrl-names = "default", "gpio";
458 pinctrl-0 = <&pinctrl_i2c1>;
459 pinctrl-1 = <&pinctrl_i2c1_gpio>;
460 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
461 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
462 status = "okay";
463
464 pca9450: pmic@25 {
465 compatible = "nxp,pca9450c";
466 interrupt-parent = <&gpio1>;
467 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
468 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_pmic>;
471 reg = <0x25>;
472
473 /*
474 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
475 * I2C level shifter for the TLA2024 ADC behind this PMIC.
476 */
477
478 regulators {
479 BUCK1 {
480 regulator-always-on;
481 regulator-boot-on;
482 regulator-max-microvolt = <1000000>;
483 regulator-min-microvolt = <720000>;
484 regulator-name = "On-module +VDD_SOC (BUCK1)";
485 regulator-ramp-delay = <3125>;
486 };
487
488 reg_vdd_arm: BUCK2 {
489 nxp,dvs-run-voltage = <950000>;
490 nxp,dvs-standby-voltage = <850000>;
491 regulator-always-on;
492 regulator-boot-on;
493 regulator-max-microvolt = <1025000>;
494 regulator-min-microvolt = <720000>;
495 regulator-name = "On-module +VDD_ARM (BUCK2)";
496 regulator-ramp-delay = <3125>;
497 };
498
499 reg_vdd_3v3: BUCK4 {
500 regulator-always-on;
501 regulator-boot-on;
502 regulator-max-microvolt = <3300000>;
503 regulator-min-microvolt = <3300000>;
504 regulator-name = "On-module +V3.3 (BUCK4)";
505 };
506
507 reg_vdd_1v8: BUCK5 {
508 regulator-always-on;
509 regulator-boot-on;
510 regulator-max-microvolt = <1800000>;
511 regulator-min-microvolt = <1800000>;
512 regulator-name = "PWR_1V8_MOCI (BUCK5)";
513 };
514
515 BUCK6 {
516 regulator-always-on;
517 regulator-boot-on;
518 regulator-max-microvolt = <1155000>;
519 regulator-min-microvolt = <1045000>;
520 regulator-name = "On-module +VDD_DDR (BUCK6)";
521 };
522
523 LDO1 {
524 regulator-always-on;
525 regulator-boot-on;
526 regulator-max-microvolt = <1950000>;
527 regulator-min-microvolt = <1650000>;
528 regulator-name = "On-module +V1.8_SNVS (LDO1)";
529 };
530
531 LDO2 {
532 regulator-always-on;
533 regulator-boot-on;
534 regulator-max-microvolt = <1150000>;
535 regulator-min-microvolt = <800000>;
536 regulator-name = "On-module +V0.8_SNVS (LDO2)";
537 };
538
539 LDO3 {
540 regulator-always-on;
541 regulator-boot-on;
542 regulator-max-microvolt = <1800000>;
543 regulator-min-microvolt = <1800000>;
544 regulator-name = "On-module +V1.8A (LDO3)";
545 };
546
547 LDO4 {
548 regulator-always-on;
549 regulator-boot-on;
550 regulator-max-microvolt = <3300000>;
551 regulator-min-microvolt = <3300000>;
552 regulator-name = "On-module +V3.3_ADC (LDO4)";
553 };
554
555 LDO5 {
556 regulator-max-microvolt = <3300000>;
557 regulator-min-microvolt = <1800000>;
558 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
559 };
560 };
561 };
562
563 rtc_i2c: rtc@32 {
564 compatible = "epson,rx8130";
565 reg = <0x32>;
566 };
567
568 /* On-module temperature sensor */
569 hwmon_temp_module: sensor@48 {
570 compatible = "ti,tmp1075";
571 reg = <0x48>;
572 vs-supply = <&reg_vdd_1v8>;
573 };
574
575 adc@49 {
576 compatible = "ti,ads1015";
577 reg = <0x49>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580
581 /* Verdin I2C_1 (ADC_4 - ADC_3) */
582 channel@0 {
583 reg = <0>;
584 ti,datarate = <4>;
585 ti,gain = <2>;
586 };
587
588 /* Verdin I2C_1 (ADC_4 - ADC_1) */
589 channel@1 {
590 reg = <1>;
591 ti,datarate = <4>;
592 ti,gain = <2>;
593 };
594
595 /* Verdin I2C_1 (ADC_3 - ADC_1) */
596 channel@2 {
597 reg = <2>;
598 ti,datarate = <4>;
599 ti,gain = <2>;
600 };
601
602 /* Verdin I2C_1 (ADC_2 - ADC_1) */
603 channel@3 {
604 reg = <3>;
605 ti,datarate = <4>;
606 ti,gain = <2>;
607 };
608
609 /* Verdin I2C_1 ADC_4 */
610 channel@4 {
611 reg = <4>;
612 ti,datarate = <4>;
613 ti,gain = <2>;
614 };
615
616 /* Verdin I2C_1 ADC_3 */
617 channel@5 {
618 reg = <5>;
619 ti,datarate = <4>;
620 ti,gain = <2>;
621 };
622
623 /* Verdin I2C_1 ADC_2 */
624 channel@6 {
625 reg = <6>;
626 ti,datarate = <4>;
627 ti,gain = <2>;
628 };
629
630 /* Verdin I2C_1 ADC_1 */
631 channel@7 {
632 reg = <7>;
633 ti,datarate = <4>;
634 ti,gain = <2>;
635 };
636 };
637
638 eeprom@50 {
639 compatible = "st,24c02";
640 pagesize = <16>;
641 reg = <0x50>;
642 };
643};
644
645/* Verdin I2C_2_DSI */
646&i2c2 {
647 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
648 clock-frequency = <10000>;
649 pinctrl-names = "default", "gpio";
650 pinctrl-0 = <&pinctrl_i2c2>;
651 pinctrl-1 = <&pinctrl_i2c2_gpio>;
652 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
653 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
654
655 atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
656 compatible = "atmel,maxtouch";
657 /* Verdin GPIO_3 (SODIMM 210) */
658 interrupt-parent = <&gpio1>;
659 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
660 reg = <0x4a>;
661 /* Verdin GPIO_2 (SODIMM 208) */
662 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
663 status = "disabled";
664 };
665};
666
667/* TODO: Verdin I2C_3_HDMI */
668
669/* Verdin I2C_4_CSI */
670&i2c3 {
671 clock-frequency = <400000>;
672 pinctrl-names = "default", "gpio";
673 pinctrl-0 = <&pinctrl_i2c3>;
674 pinctrl-1 = <&pinctrl_i2c3_gpio>;
675 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
676 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
677};
678
679/* Verdin I2C_1 */
680&i2c4 {
681 clock-frequency = <400000>;
682 pinctrl-names = "default", "gpio";
683 pinctrl-0 = <&pinctrl_i2c4>;
684 pinctrl-1 = <&pinctrl_i2c4_gpio>;
685 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
686 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
687
688 gpio_expander_21: gpio-expander@21 {
689 compatible = "nxp,pcal6416";
690 #gpio-cells = <2>;
691 gpio-controller;
692 reg = <0x21>;
693 vcc-supply = <&reg_3p3v>;
694 status = "disabled";
695 };
696
697 lvds_ti_sn65dsi84: bridge@2c {
698 compatible = "ti,sn65dsi84";
699 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
700 /* Verdin GPIO_10_DSI (SODIMM 21) */
701 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
704 reg = <0x2c>;
705 status = "disabled";
706 };
707
708 /* Current measurement into module VCC */
709 hwmon: hwmon@40 {
710 compatible = "ti,ina219";
711 reg = <0x40>;
712 shunt-resistor = <10000>;
713 status = "disabled";
714 };
715
716 hdmi_lontium_lt8912: hdmi@48 {
717 compatible = "lontium,lt8912b";
718 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
720 reg = <0x48>;
721 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
722 /* Verdin GPIO_10_DSI (SODIMM 21) */
723 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
724 status = "disabled";
725 };
726
727 atmel_mxt_ts: touch@4a {
728 compatible = "atmel,maxtouch";
729 /*
730 * Verdin GPIO_9_DSI
731 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
732 */
733 interrupt-parent = <&gpio4>;
734 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
737 reg = <0x4a>;
738 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
739 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
740 status = "disabled";
741 };
742
743 /* Temperature sensor on carrier board */
744 hwmon_temp: sensor@4f {
745 compatible = "ti,tmp75c";
746 reg = <0x4f>;
747 status = "disabled";
748 };
749
750 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
751 eeprom_display_adapter: eeprom@50 {
752 compatible = "st,24c02";
753 pagesize = <16>;
754 reg = <0x50>;
755 status = "disabled";
756 };
757
758 /* EEPROM on carrier board */
759 eeprom_carrier_board: eeprom@57 {
760 compatible = "st,24c02";
761 pagesize = <16>;
762 reg = <0x57>;
763 status = "disabled";
764 };
765};
766
767/* Verdin PCIE_1 */
768&pcie {
769 pinctrl-names = "default";
770 pinctrl-0 = <&pinctrl_pcie>;
771 /* PCIE_1_RESET# (SODIMM 244) */
772 reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
773};
774
775&pcie_phy {
776 clocks = <&hsio_blk_ctrl>;
777 clock-names = "ref";
778 fsl,clkreq-unsupported;
779 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
780};
781
782/* Verdin PWM_1 */
783&pwm1 {
784 pinctrl-names = "default";
785 pinctrl-0 = <&pinctrl_pwm_1>;
786 #pwm-cells = <3>;
787};
788
789/* Verdin PWM_2 */
790&pwm2 {
791 pinctrl-names = "default";
792 pinctrl-0 = <&pinctrl_pwm_2>;
793 #pwm-cells = <3>;
794};
795
796/* Verdin PWM_3_DSI */
797&pwm3 {
798 pinctrl-names = "default";
799 pinctrl-0 = <&pinctrl_pwm_3>;
800 #pwm-cells = <3>;
801};
802
803/* TODO: Verdin I2S_1 */
804
805/* TODO: Verdin I2S_2 */
806
807&snvs_pwrkey {
808 status = "okay";
809};
810
811/* Verdin UART_1 */
812&uart1 {
813 pinctrl-names = "default";
814 pinctrl-0 = <&pinctrl_uart1>;
815 uart-has-rtscts;
816};
817
818/* Verdin UART_2 */
819&uart2 {
820 pinctrl-names = "default";
821 pinctrl-0 = <&pinctrl_uart2>;
822 uart-has-rtscts;
823};
824
825/* Verdin UART_3, used as the Linux Console */
826&uart3 {
827 pinctrl-names = "default";
828 pinctrl-0 = <&pinctrl_uart3>;
829};
830
831/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
832&uart4 {
833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_uart4>;
835};
836
837/* Verdin USB_1 */
838&usb3_0 {
839 fsl,disable-port-power-control;
840 fsl,over-current-active-low;
841 pinctrl-names = "default";
842 pinctrl-0 = <&pinctrl_usb_1_oc_n>;
843};
844
845&usb_dwc3_0 {
846 /* dual role only, not full featured OTG */
847 adp-disable;
848 dr_mode = "otg";
849 hnp-disable;
850 maximum-speed = "high-speed";
851 role-switch-default-mode = "peripheral";
852 srp-disable;
853 usb-role-switch;
854
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame^]855 port {
856 usb3_dwc: endpoint {
857 remote-endpoint = <&usb_dr_connector>;
858 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]859 };
860};
861
862/* Verdin USB_2 */
863&usb3_1 {
864 fsl,disable-port-power-control;
865};
866
867&usb3_phy1 {
868 vbus-supply = <&reg_usb2_vbus>;
869};
870
871&usb_dwc3_1 {
872 dr_mode = "host";
873};
874
875/* Verdin SD_1 */
876&usdhc2 {
877 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
878 assigned-clock-rates = <400000000>;
879 bus-width = <4>;
880 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
881 disable-wp;
882 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
883 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
884 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
885 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
886 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
887 vmmc-supply = <&reg_usdhc2_vmmc>;
888};
889
890/* On-module eMMC */
891&usdhc3 {
892 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
893 assigned-clock-rates = <400000000>;
894 bus-width = <8>;
895 non-removable;
896 pinctrl-names = "default", "state_100mhz", "state_200mhz";
897 pinctrl-0 = <&pinctrl_usdhc3>;
898 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
899 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
900 status = "okay";
901};
902
903&wdog1 {
904 fsl,ext-reset-output;
905 pinctrl-names = "default";
906 pinctrl-0 = <&pinctrl_wdog>;
907 status = "okay";
908};
909
910&iomuxc {
911 pinctrl_bt_uart: btuartgrp {
912 fsl,pins =
913 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>,
914 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>,
915 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>,
916 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>;
917 };
918
919 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
920 fsl,pins =
921 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */
922 };
923
924 pinctrl_ecspi1: ecspi1grp {
925 fsl,pins =
926 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */
927 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */
928 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */
929 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */
930 };
931
932 /* Connection On Board PHY */
933 pinctrl_eqos: eqosgrp {
934 fsl,pins =
935 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
936 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
937 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
938 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
939 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
940 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
941 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
942 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
943 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
944 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
945 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
946 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
947 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
948 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
949 };
950
951 /* ETH_INT# shared with TPM_INT# (usually N/A) */
952 pinctrl_eth_tpm_int: ethtpmintgrp {
953 fsl,pins =
954 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>;
955 };
956
957 /* Connection Carrier Board PHY ETH_2 */
958 pinctrl_fec: fecgrp {
959 fsl,pins =
960 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
961 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
962 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
963 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
964 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
965 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
966 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
967 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
968 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */
969 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */
970 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */
971 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */
972 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */
973 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */
974 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */
975 };
976
977 pinctrl_fec_sleep: fecsleepgrp {
978 fsl,pins =
979 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
980 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
981 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
982 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
983 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
984 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
985 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
986 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
987 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */
988 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */
989 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */
990 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */
991 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */
992 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */
993 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */
994 };
995
996 pinctrl_flexcan1: flexcan1grp {
997 fsl,pins =
998 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */
999 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */
1000 };
1001
1002 pinctrl_flexcan2: flexcan2grp {
1003 fsl,pins =
1004 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */
1005 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */
1006 };
1007
1008 pinctrl_flexspi0: flexspi0grp {
1009 fsl,pins =
1010 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
1011 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
1012 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
1013 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
1014 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
1015 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
1016 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
1017 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
1018 };
1019
1020 pinctrl_gpio1: gpio1grp {
1021 fsl,pins =
1022 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */
1023 };
1024
1025 pinctrl_gpio2: gpio2grp {
1026 fsl,pins =
1027 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */
1028 };
1029
1030 pinctrl_gpio3: gpio3grp {
1031 fsl,pins =
1032 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */
1033 };
1034
1035 pinctrl_gpio4: gpio4grp {
1036 fsl,pins =
1037 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */
1038 };
1039
1040 pinctrl_gpio5: gpio5grp {
1041 fsl,pins =
1042 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */
1043 };
1044
1045 pinctrl_gpio6: gpio6grp {
1046 fsl,pins =
1047 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */
1048 };
1049
1050 pinctrl_gpio7: gpio7grp {
1051 fsl,pins =
1052 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */
1053 };
1054
1055 pinctrl_gpio8: gpio8grp {
1056 fsl,pins =
1057 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */
1058 };
1059
1060 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
1061 pinctrl_gpio_9_dsi: gpio9dsigrp {
1062 fsl,pins =
1063 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */
1064 };
1065
1066 /* Verdin GPIO_10_DSI */
1067 pinctrl_gpio_10_dsi: gpio10dsigrp {
1068 fsl,pins =
1069 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */
1070 };
1071
1072 /* Non-wifi MSP usage only */
1073 pinctrl_gpio_hog1: gpiohog1grp {
1074 fsl,pins =
1075 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */
1076 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */
1077 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */
1078 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */
1079 };
1080
1081 /* USB_2_OC# */
1082 pinctrl_gpio_hog2: gpiohog2grp {
1083 fsl,pins =
1084 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */
1085 };
1086
1087 pinctrl_gpio_hog3: gpiohog3grp {
1088 fsl,pins =
1089 /* CSI_1_MCLK */
1090 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
1091 };
1092
1093 /* Wifi usage only */
1094 pinctrl_gpio_hog4: gpiohog4grp {
1095 fsl,pins =
1096 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */
1097 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */
1098 };
1099
1100 pinctrl_gpio_keys: gpiokeysgrp {
1101 fsl,pins =
1102 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
1103 };
1104
1105 pinctrl_hdmi_hog: hdmihoggrp {
1106 fsl,pins =
1107 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
1108 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
1109 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
1110 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
1111 };
1112
1113 /* On-module I2C */
1114 pinctrl_i2c1: i2c1grp {
1115 fsl,pins =
1116 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
1117 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
1118 };
1119
1120 pinctrl_i2c1_gpio: i2c1gpiogrp {
1121 fsl,pins =
1122 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
1123 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
1124 };
1125
1126 /* Verdin I2C_2_DSI */
1127 pinctrl_i2c2: i2c2grp {
1128 fsl,pins =
1129 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */
1130 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */
1131 };
1132
1133 pinctrl_i2c2_gpio: i2c2gpiogrp {
1134 fsl,pins =
1135 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
1136 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
1137 };
1138
1139 /* Verdin I2C_4_CSI */
1140 pinctrl_i2c3: i2c3grp {
1141 fsl,pins =
1142 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */
1143 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */
1144 };
1145
1146 pinctrl_i2c3_gpio: i2c3gpiogrp {
1147 fsl,pins =
1148 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
1149 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
1150 };
1151
1152 /* Verdin I2C_1 */
1153 pinctrl_i2c4: i2c4grp {
1154 fsl,pins =
1155 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */
1156 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */
1157 };
1158
1159 pinctrl_i2c4_gpio: i2c4gpiogrp {
1160 fsl,pins =
1161 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
1162 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
1163 };
1164
1165 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1166 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1167 fsl,pins =
1168 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */
1169 };
1170
1171 /* Verdin I2S_2_D_OUT shared with SAI3 */
1172 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1173 fsl,pins =
1174 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */
1175 };
1176
1177 pinctrl_pcie: pciegrp {
1178 fsl,pins =
1179 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */
1180 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1181 };
1182
1183 pinctrl_pmic: pmicirqgrp {
1184 fsl,pins =
1185 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
1186 };
1187
1188 pinctrl_pwm_1: pwm1grp {
1189 fsl,pins =
1190 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */
1191 };
1192
1193 pinctrl_pwm_2: pwm2grp {
1194 fsl,pins =
1195 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */
1196 };
1197
1198 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1199 pinctrl_pwm_3: pwm3grp {
1200 fsl,pins =
1201 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */
1202 };
1203
1204 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1205 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1206 fsl,pins =
1207 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */
1208 };
1209
1210 pinctrl_reg_eth: regethgrp {
1211 fsl,pins =
1212 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
1213 };
1214
1215 pinctrl_sai1: sai1grp {
1216 fsl,pins =
1217 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
1218 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
1219 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
1220 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
1221 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
1222 };
1223
1224 pinctrl_sai3: sai3grp {
1225 fsl,pins =
1226 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1227 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */
1228 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */
1229 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */
1230 };
1231
1232 pinctrl_uart1: uart1grp {
1233 fsl,pins =
1234 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */
1235 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */
1236 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */
1237 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
1238 };
1239
1240 pinctrl_uart2: uart2grp {
1241 fsl,pins =
1242 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
1243 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
1244 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
1245 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
1246 };
1247
1248 pinctrl_uart3: uart3grp {
1249 fsl,pins =
1250 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */
1251 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */
1252 };
1253
1254 /* Non-wifi usage only */
1255 pinctrl_uart4: uart4grp {
1256 fsl,pins =
1257 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
1258 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
1259 };
1260
1261 pinctrl_usb1_vbus: usb1vbusgrp {
1262 fsl,pins =
1263 <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */
1264 };
1265
1266 /* USB_1_ID */
1267 pinctrl_usb_1_id: usb1idgrp {
1268 fsl,pins =
1269 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
1270 };
1271
1272 /* USB_1_OC# */
1273 pinctrl_usb_1_oc_n: usb1ocngrp {
1274 fsl,pins =
1275 <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */
1276 };
1277
1278 pinctrl_usb2_vbus: usb2vbusgrp {
1279 fsl,pins =
1280 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */
1281 };
1282
1283 /* On-module Wi-Fi */
1284 pinctrl_usdhc1: usdhc1grp {
1285 fsl,pins =
1286 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>,
1287 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>,
1288 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>,
1289 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>,
1290 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>,
1291 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>;
1292 };
1293
1294 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1295 fsl,pins =
1296 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>,
1297 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>,
1298 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>,
1299 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>,
1300 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>,
1301 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>;
1302 };
1303
1304 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1305 fsl,pins =
1306 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>,
1307 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>,
1308 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>,
1309 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>,
1310 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>,
1311 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>;
1312 };
1313
1314 pinctrl_usdhc2_cd: usdhc2cdgrp {
1315 fsl,pins =
1316 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */
1317 };
1318
1319 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1320 fsl,pins =
1321 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */
1322 };
1323
1324 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1325 fsl,pins =
1326 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */
1327 };
1328
1329 pinctrl_usdhc2: usdhc2grp {
1330 fsl,pins =
1331 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */
1332 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */
1333 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */
1334 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
1335 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
1336 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
1337 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */
1338 };
1339
1340 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1341 fsl,pins =
1342 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1343 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
1344 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
1345 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
1346 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
1347 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
1348 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
1349 };
1350
1351 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1352 fsl,pins =
1353 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1354 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
1355 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
1356 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
1357 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
1358 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
1359 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>;
1360 };
1361
1362 /* Avoid backfeeding with removed card power */
1363 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1364 fsl,pins =
1365 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>,
1366 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>,
1367 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>,
1368 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>,
1369 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>,
1370 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>,
1371 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>;
1372 };
1373
1374 pinctrl_usdhc3: usdhc3grp {
1375 fsl,pins =
1376 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1377 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>,
1378 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
1379 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
1380 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
1381 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
1382 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
1383 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
1384 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
1385 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
1386 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
1387 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>;
1388 };
1389
1390 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1391 fsl,pins =
1392 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1393 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>,
1394 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
1395 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
1396 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
1397 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
1398 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
1399 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
1400 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
1401 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
1402 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
1403 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>;
1404 };
1405
1406 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1407 fsl,pins =
1408 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1409 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>,
1410 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>,
1411 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>,
1412 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>,
1413 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>,
1414 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>,
1415 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>,
1416 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>,
1417 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>,
1418 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
1419 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>;
1420 };
1421
1422 pinctrl_wdog: wdoggrp {
1423 fsl,pins =
1424 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
1425 };
1426
1427 pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1428 fsl,pins =
1429 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */
1430 };
1431
1432 pinctrl_wifi_ctrl: wifictrlgrp {
1433 fsl,pins =
1434 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */
1435 };
1436
1437 pinctrl_wifi_i2s: wifii2sgrp {
1438 fsl,pins =
1439 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */
1440 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */
1441 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */
1442 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */
1443 };
1444
1445 pinctrl_wifi_pwr_en: wifipwrengrp {
1446 fsl,pins =
1447 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */
1448 };
1449};