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wdenk281e00a2004-08-01 22:48:16 +00001/*
2 * Copyright (C) 2004 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
24#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
25#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */
26#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
27
28/*
29 * Select serial console configuration
30 */
31#undef _CONFIG_UART1 /* internal uart 1 */
32#define _CONFIG_UART2 /* internal uart 2 */
33#undef _CONFIG_UART3 /* internal uart 3 */
34#undef _CONFIG_UART4 /* internal uart 4 */
35#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
36
wdenk281e00a2004-08-01 22:48:16 +000037
Jon Loeliger5dc11a52007-07-04 22:33:01 -050038/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050039 * BOOTP options
40 */
41#define CONFIG_BOOTP_BOOTFILESIZE
42#define CONFIG_BOOTP_BOOTPATH
43#define CONFIG_BOOTP_GATEWAY
44#define CONFIG_BOOTP_HOSTNAME
45
46
47/*
Jon Loeliger5dc11a52007-07-04 22:33:01 -050048 * Command line configuration.
49 */
50#include <config_cmd_default.h>
51
52#define CONFIG_CMD_JFFS2
53
Jon Loeliger5dc11a52007-07-04 22:33:01 -050054#undef CONFIG_CMD_CONSOLE
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020055#undef CONFIG_CMD_DHCP
56#undef CONFIG_CMD_LOADS
Jon Loeliger5dc11a52007-07-04 22:33:01 -050057#undef CONFIG_CMD_NET
58#undef CONFIG_CMD_PING
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020059#undef CONFIG_CMD_SOURCE
Jon Loeliger5dc11a52007-07-04 22:33:01 -050060
wdenk281e00a2004-08-01 22:48:16 +000061
62/*
63 * Boot options. Setting delay to -1 stops autostart count down.
64 */
65#define CONFIG_BOOTDELAY 10
66#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2"
67#define CONFIG_BOOTCOMMAND "bootm 10080000"
68#define CONFIG_SHOW_BOOT_PROGRESS
69
70/*
71 * General options for u-boot. Modify to save memory foot print
72 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_LONGHELP /* undef saves memory */
74#define CONFIG_SYS_PROMPT "mx1fs2> " /* prompt string */
75#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
76#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
77#define CONFIG_SYS_MAXARGS 16 /* max command args */
78#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
wdenk281e00a2004-08-01 22:48:16 +000079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
81#define CONFIG_SYS_MEMTEST_END 0x08F00000
wdenk281e00a2004-08-01 22:48:16 +000082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
84#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
wdenk281e00a2004-08-01 22:48:16 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk281e00a2004-08-01 22:48:16 +000087#define CONFIG_BAUDRATE 115200
88/*
89 * Definitions related to passing arguments to kernel.
90 */
91#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
92#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
93#define CONFIG_INITRD_TAG 1 /* send initrd params */
94#undef CONFIG_VFD /* do not send framebuffer setup */
95
wdenk281e00a2004-08-01 22:48:16 +000096/*
97 * Malloc pool need to host env + 128 Kb reserve for other allocations.
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
wdenk281e00a2004-08-01 22:48:16 +0000100
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk281e00a2004-08-01 22:48:16 +0000103
104#define CONFIG_STACKSIZE (120<<10) /* stack size */
105
106#ifdef CONFIG_USE_IRQ
107#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
108#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
109#endif
110
111/* SDRAM Setup Values
112 * 0x910a8300 Precharge Command CAS 3
113 * 0x910a8200 Precharge Command CAS 2
114 *
115 * 0xa10a8300 AutoRefresh Command CAS 3
116 * 0xa10a8200 Set AutoRefresh Command CAS 2
117 */
118#define PRECHARGE_CMD 0x910a8300
119#define AUTOREFRESH_CMD 0xa10a8300
120
wdenk281e00a2004-08-01 22:48:16 +0000121#define BUS32BIT_VERSION
122/*
123 * SDRAM Memory Map
124 */
125#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
126#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */
127#ifdef BUS32BIT_VERSION
128#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */
129#else
130#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */
131#endif
132/*
133 * Flash Controller settings
134 */
135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
137#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
wdenk281e00a2004-08-01 22:48:16 +0000138
139#ifdef BUS32BIT_VERSION
140#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
141#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
142#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/
143#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
wdenk281e00a2004-08-01 22:48:16 +0000144#else
145#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
146#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
147#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/
148#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */
149#endif
150#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */
151#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */
152
153/* This should be defined if CFI FLASH device is present. Actually benefit
154 is not so clear to me. In other words we can provide more informations
155 to user, but this expects more complex flash handling we do not provide
156 now.*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#undef CONFIG_SYS_FLASH_CFI
wdenk281e00a2004-08-01 22:48:16 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */
160#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */
wdenk281e00a2004-08-01 22:48:16 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_BASE MX1FS2_FLASH_BASE
wdenk281e00a2004-08-01 22:48:16 +0000163
164/*
165 * This is setting for JFFS2 support in u-boot.
166 * Right now there is no gain for user, but later on booting kernel might be
167 * possible. Consider using XIP kernel running from flash to save RAM
168 * footprint.
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500169 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
wdenk281e00a2004-08-01 22:48:16 +0000170 */
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200171
172/*
173 * JFFS2 partitions
174 */
175/* No command line, one static partition, whole device */
176/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100177#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200178#define CONFIG_JFFS2_DEV "nor0"
179#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
180#define CONFIG_JFFS2_PART_OFFSET 0x00050000
181*/
182
183/* mtdparts command line support */
184/* Note: fake mtd_id used, no linux mtd map file */
Stefan Roese68d7d652009-03-19 13:30:36 +0100185#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200186#define MTDIDS_DEFAULT "nor0=mx1fs2-0"
187
188#ifdef BUS32BIT_VERSION
189#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)"
190#else
191#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:-@320k(jffs2)"
192#endif
wdenk281e00a2004-08-01 22:48:16 +0000193
194/*
195 * Environment setup. Definitions of monitor location and size with
196 * definition of environment setup ends up in 2 possibilities.
197 * 1. Embeded environment - in u-boot code is space for environment
198 * 2. Environment is read from predefined sector of flash
199 * Right now we support 2. possiblity, but expecting no env placed
200 * on mentioned address right now. This also needs to provide whole
201 * sector for it - for us 256Kb is really waste of memory. U-boot uses
202 * default env. and until kernel parameters could be sent to kernel
203 * env. has no sense to us.
204 */
205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_MONITOR_BASE 0x10000000
207#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200208#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200209#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
210#define CONFIG_ENV_SIZE 0x20000
wdenk281e00a2004-08-01 22:48:16 +0000211
212#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
213
214/* Setup CS4 and CS5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_GIUS_A_VAL 0x0003fffe
wdenk281e00a2004-08-01 22:48:16 +0000216
217/*
218 * CSxU_VAL:
219 * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
220 * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
221 *
222 * CSxL_VAL:
223 * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
224 * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
225 */
226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_CS0U_VAL 0x00008C00
228#define CONFIG_SYS_CS0L_VAL 0x22222601
229#define CONFIG_SYS_CS1U_VAL 0x00008C00
230#define CONFIG_SYS_CS1L_VAL 0x22222301
231#define CONFIG_SYS_CS4U_VAL 0x00008C00
232#define CONFIG_SYS_CS4L_VAL 0x22222301
233#define CONFIG_SYS_CS5U_VAL 0x00008C00
234#define CONFIG_SYS_CS5L_VAL 0x22222301
wdenk281e00a2004-08-01 22:48:16 +0000235
236/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
237 f_ref=16,777MHz
238
239 0x002a141f: 191,9944MHz
240 0x040b2007: 144MHz
241 0x042a141f: 96MHz
242 0x0811140d: 64MHz
243 0x040e200e: 150MHz
244 0x00321431: 200MHz
245
246 0x08001800: 64MHz mit 16er Quarz
247 0x04001800: 96MHz mit 16er Quarz
248 0x04002400: 144MHz mit 16er Quarz
249
250 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
251 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_MPCTL0_VAL 0x07E723AD
254#define CONFIG_SYS_MPCTL1_VAL 0x00000040
255#define CONFIG_SYS_PCDR_VAL 0x00010005
256#define CONFIG_SYS_GPCR_VAL 0x00000FFB
wdenk281e00a2004-08-01 22:48:16 +0000257
258#define USE_16M_OSZI /* If you have one, you want to use it
259 The internal 32kHz oszillator jitters */
260#ifdef USE_16M_OSZI
261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_SPCTL0_VAL 0x04001401
263#define CONFIG_SYS_SPCTL1_VAL 0x0C000040
264#define CONFIG_SYS_CSCR_VAL 0x07030003
wdenk281e00a2004-08-01 22:48:16 +0000265#define CONFIG_SYS_CLK_FREQ 16780000
266#define CONFIG_SYSPLL_CLK_FREQ 16000000
267
268#else
269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SPCTL0_VAL 0x07E716D1
271#define CONFIG_SYS_CSCR_VAL 0x06000003
wdenk281e00a2004-08-01 22:48:16 +0000272#define CONFIG_SYS_CLK_FREQ 16780000
273#define CONFIG_SYSPLL_CLK_FREQ 16780000
274
275#endif
276
277/*
278 * Well this has to be defined, but on the other hand it is used differently
279 * one may expect. For instance loadb command do not cares :-)
280 * So advice is - do not relay on this...
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_LOAD_ADDR 0x08400000
wdenk281e00a2004-08-01 22:48:16 +0000283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_FMCR_VAL 0x00000003 /* Reset Default */
wdenk281e00a2004-08-01 22:48:16 +0000285
286/* Bit[0:3] contain PERCLK1DIV for UART 1
287 0x000b00b ->b<- -> 192MHz/12=16MHz
288 0x000b00b ->8<- -> 144MHz/09=16MHz
289 0x000b00b ->3<- -> 64MHz/4=16MHz */
290
291#ifdef _CONFIG_UART1
Jean-Christophe PLAGNIOL-VILLARDd3e55d02009-03-30 18:58:38 +0200292#define CONFIG_IMX_SERIAL
wdenk281e00a2004-08-01 22:48:16 +0000293#define CONFIG_IMX_SERIAL1
294#elif defined _CONFIG_UART2
Jean-Christophe PLAGNIOL-VILLARDd3e55d02009-03-30 18:58:38 +0200295#define CONFIG_IMX_SERIAL
wdenk281e00a2004-08-01 22:48:16 +0000296#define CONFIG_IMX_SERIAL2
297#elif defined _CONFIG_UART3 | defined _CONFIG_UART4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_NS16550
299#define CONFIG_SYS_NS16550_SERIAL
300#define CONFIG_SYS_NS16550_CLK 3686400
301#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk281e00a2004-08-01 22:48:16 +0000302#define CONFIG_CONS_INDEX 1
303#ifdef _CONFIG_UART3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_NS16550_COM1 0x15000000
wdenk281e00a2004-08-01 22:48:16 +0000305#elif defined _CONFIG_UART4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_NS16550_COM1 0x16000000
wdenk281e00a2004-08-01 22:48:16 +0000307#endif
308#endif
309
310#endif /* __CONFIG_H */