blob: 5740379841483267bd57ae4b9ae4c895f15cfffd [file] [log] [blame]
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001/*
2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Ilya Yanok0b23fb32009-07-21 19:32:21 +04009 */
10
11#include <common.h>
Jagan Teki60752ca2016-12-06 00:00:49 +010012#include <dm.h>
Alex Kiernan9925f1d2018-04-01 09:22:38 +000013#include <environment.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040014#include <malloc.h>
Simon Glasscf92e052015-09-02 17:24:58 -060015#include <memalign.h>
Jagan Teki567173a2016-12-06 00:00:50 +010016#include <miiphy.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040017#include <net.h>
Jeroen Hofstee84f64c82014-10-08 22:57:40 +020018#include <netdev.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040019#include "fec_mxc.h"
20
Jagan Teki567173a2016-12-06 00:00:50 +010021#include <asm/io.h>
22#include <linux/errno.h>
23#include <linux/compiler.h>
24
Ilya Yanok0b23fb32009-07-21 19:32:21 +040025#include <asm/arch/clock.h>
26#include <asm/arch/imx-regs.h>
Stefano Babic552a8482017-06-29 10:16:06 +020027#include <asm/mach-imx/sys_proto.h>
Ilya Yanok0b23fb32009-07-21 19:32:21 +040028
29DECLARE_GLOBAL_DATA_PTR;
30
Marek Vasutbc1ce152012-08-29 03:49:49 +000031/*
32 * Timeout the transfer after 5 mS. This is usually a bit more, since
33 * the code in the tightloops this timeout is used in adds some overhead.
34 */
35#define FEC_XFER_TIMEOUT 5000
36
Fabio Estevamdb5b7f52014-08-25 13:34:16 -030037/*
38 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
39 * 64-byte alignment in the DMA RX FEC buffer.
40 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
41 * satisfies the alignment on other SoCs (32-bytes)
42 */
43#define FEC_DMA_RX_MINALIGN 64
44
Ilya Yanok0b23fb32009-07-21 19:32:21 +040045#ifndef CONFIG_MII
46#error "CONFIG_MII has to be defined!"
47#endif
48
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000049#ifndef CONFIG_FEC_XCV_TYPE
50#define CONFIG_FEC_XCV_TYPE MII100
Marek Vasut392b8502011-09-11 18:05:33 +000051#endif
52
Marek Vasutbe7e87e2011-11-08 23:18:10 +000053/*
54 * The i.MX28 operates with packets in big endian. We need to swap them before
55 * sending and after receiving.
56 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000057#ifdef CONFIG_MX28
58#define CONFIG_FEC_MXC_SWAP_PACKET
59#endif
60
61#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
62
63/* Check various alignment issues at compile time */
64#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
65#error "ARCH_DMA_MINALIGN must be multiple of 16!"
66#endif
67
68#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
69 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
70#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
Marek Vasutbe7e87e2011-11-08 23:18:10 +000071#endif
72
Ilya Yanok0b23fb32009-07-21 19:32:21 +040073#undef DEBUG
74
Eric Nelson5c1ad3e2012-03-15 18:33:25 +000075#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +000076static void swap_packet(uint32_t *packet, int length)
77{
78 int i;
79
80 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
81 packet[i] = __swab32(packet[i]);
82}
83#endif
84
Jagan Teki567173a2016-12-06 00:00:50 +010085/* MII-interface related functions */
86static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
87 uint8_t regaddr)
Ilya Yanok0b23fb32009-07-21 19:32:21 +040088{
Ilya Yanok0b23fb32009-07-21 19:32:21 +040089 uint32_t reg; /* convenient holder for the PHY register */
90 uint32_t phy; /* convenient holder for the PHY */
91 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +000092 int val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +040093
94 /*
95 * reading from any PHY's register is done by properly
96 * programming the FEC's MII data register.
97 */
Marek Vasutd133b882011-09-11 18:05:34 +000098 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Teki567173a2016-12-06 00:00:50 +010099 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
100 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400101
102 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
Marek Vasutd133b882011-09-11 18:05:34 +0000103 phy | reg, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400104
Jagan Teki567173a2016-12-06 00:00:50 +0100105 /* wait for the related interrupt */
Graeme Russa60d1e52011-07-15 23:31:37 +0000106 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000107 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400108 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
109 printf("Read MDIO failed...\n");
110 return -1;
111 }
112 }
113
Jagan Teki567173a2016-12-06 00:00:50 +0100114 /* clear mii interrupt bit */
Marek Vasutd133b882011-09-11 18:05:34 +0000115 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400116
Jagan Teki567173a2016-12-06 00:00:50 +0100117 /* it's now safe to read the PHY's register */
Troy Kisky13947f42012-02-07 14:08:47 +0000118 val = (unsigned short)readl(&eth->mii_data);
Jagan Teki567173a2016-12-06 00:00:50 +0100119 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
120 regaddr, val);
Troy Kisky13947f42012-02-07 14:08:47 +0000121 return val;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400122}
123
Troy Kisky575c5cc2012-10-22 16:40:41 +0000124static void fec_mii_setspeed(struct ethernet_regs *eth)
Stefano Babic4294b242010-02-01 14:51:30 +0100125{
126 /*
127 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
128 * and do not drop the Preamble.
Måns Rullgård843a3e52015-12-08 15:38:45 +0000129 *
130 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
131 * MII_SPEED) register that defines the MDIO output hold time. Earlier
132 * versions are RAZ there, so just ignore the difference and write the
133 * register always.
134 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
135 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
136 * output.
137 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
138 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
139 * holdtime cannot result in a value greater than 3.
Stefano Babic4294b242010-02-01 14:51:30 +0100140 */
Måns Rullgård843a3e52015-12-08 15:38:45 +0000141 u32 pclk = imx_get_fecclk();
142 u32 speed = DIV_ROUND_UP(pclk, 5000000);
143 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
Markus Niebel6ba45cc2014-02-05 10:54:11 +0100144#ifdef FEC_QUIRK_ENET_MAC
145 speed--;
146#endif
Måns Rullgård843a3e52015-12-08 15:38:45 +0000147 writel(speed << 1 | hold << 8, &eth->mii_speed);
Troy Kisky575c5cc2012-10-22 16:40:41 +0000148 debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
Stefano Babic4294b242010-02-01 14:51:30 +0100149}
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400150
Jagan Teki567173a2016-12-06 00:00:50 +0100151static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
152 uint8_t regaddr, uint16_t data)
Troy Kisky13947f42012-02-07 14:08:47 +0000153{
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400154 uint32_t reg; /* convenient holder for the PHY register */
155 uint32_t phy; /* convenient holder for the PHY */
156 uint32_t start;
157
Jagan Teki567173a2016-12-06 00:00:50 +0100158 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
159 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400160
161 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
Marek Vasutd133b882011-09-11 18:05:34 +0000162 FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400163
Jagan Teki567173a2016-12-06 00:00:50 +0100164 /* wait for the MII interrupt */
Graeme Russa60d1e52011-07-15 23:31:37 +0000165 start = get_timer(0);
Marek Vasutd133b882011-09-11 18:05:34 +0000166 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400167 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
168 printf("Write MDIO failed...\n");
169 return -1;
170 }
171 }
172
Jagan Teki567173a2016-12-06 00:00:50 +0100173 /* clear MII interrupt bit */
Marek Vasutd133b882011-09-11 18:05:34 +0000174 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Teki567173a2016-12-06 00:00:50 +0100175 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
176 regaddr, data);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400177
178 return 0;
179}
180
Jagan Teki567173a2016-12-06 00:00:50 +0100181static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
182 int regaddr)
Troy Kisky13947f42012-02-07 14:08:47 +0000183{
Jagan Teki567173a2016-12-06 00:00:50 +0100184 return fec_mdio_read(bus->priv, phyaddr, regaddr);
Troy Kisky13947f42012-02-07 14:08:47 +0000185}
186
Jagan Teki567173a2016-12-06 00:00:50 +0100187static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
188 int regaddr, u16 data)
Troy Kisky13947f42012-02-07 14:08:47 +0000189{
Jagan Teki567173a2016-12-06 00:00:50 +0100190 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
Troy Kisky13947f42012-02-07 14:08:47 +0000191}
192
193#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400194static int miiphy_restart_aneg(struct eth_device *dev)
195{
Stefano Babicb774fe92012-02-22 00:24:35 +0000196 int ret = 0;
197#if !defined(CONFIG_FEC_MXC_NO_ANEG)
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200198 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000199 struct ethernet_regs *eth = fec->bus->priv;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200200
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400201 /*
202 * Wake up from sleep if necessary
203 * Reset PHY, then delay 300ns
204 */
John Rigbycb17b922010-01-25 23:12:55 -0700205#ifdef CONFIG_MX27
Troy Kisky13947f42012-02-07 14:08:47 +0000206 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
John Rigbycb17b922010-01-25 23:12:55 -0700207#endif
Troy Kisky13947f42012-02-07 14:08:47 +0000208 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400209 udelay(1000);
210
Jagan Teki567173a2016-12-06 00:00:50 +0100211 /* Set the auto-negotiation advertisement register bits */
Troy Kisky13947f42012-02-07 14:08:47 +0000212 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
Jagan Teki567173a2016-12-06 00:00:50 +0100213 LPA_100FULL | LPA_100HALF | LPA_10FULL |
214 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
Troy Kisky13947f42012-02-07 14:08:47 +0000215 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
Jagan Teki567173a2016-12-06 00:00:50 +0100216 BMCR_ANENABLE | BMCR_ANRESTART);
Marek Vasut2e5f4422011-09-11 18:05:36 +0000217
218 if (fec->mii_postcall)
219 ret = fec->mii_postcall(fec->phy_id);
220
Stefano Babicb774fe92012-02-22 00:24:35 +0000221#endif
Marek Vasut2e5f4422011-09-11 18:05:36 +0000222 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400223}
224
Hannes Schmelzer07507012016-06-22 12:07:14 +0200225#ifndef CONFIG_FEC_FIXED_SPEED
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400226static int miiphy_wait_aneg(struct eth_device *dev)
227{
228 uint32_t start;
Troy Kisky13947f42012-02-07 14:08:47 +0000229 int status;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200230 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky13947f42012-02-07 14:08:47 +0000231 struct ethernet_regs *eth = fec->bus->priv;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400232
Jagan Teki567173a2016-12-06 00:00:50 +0100233 /* Wait for AN completion */
Graeme Russa60d1e52011-07-15 23:31:37 +0000234 start = get_timer(0);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400235 do {
236 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
237 printf("%s: Autonegotiation timeout\n", dev->name);
238 return -1;
239 }
240
Troy Kisky13947f42012-02-07 14:08:47 +0000241 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
242 if (status < 0) {
243 printf("%s: Autonegotiation failed. status: %d\n",
Jagan Teki567173a2016-12-06 00:00:50 +0100244 dev->name, status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400245 return -1;
246 }
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500247 } while (!(status & BMSR_LSTATUS));
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400248
249 return 0;
250}
Hannes Schmelzer07507012016-06-22 12:07:14 +0200251#endif /* CONFIG_FEC_FIXED_SPEED */
Troy Kisky13947f42012-02-07 14:08:47 +0000252#endif
253
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400254static int fec_rx_task_enable(struct fec_priv *fec)
255{
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000256 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400257 return 0;
258}
259
260static int fec_rx_task_disable(struct fec_priv *fec)
261{
262 return 0;
263}
264
265static int fec_tx_task_enable(struct fec_priv *fec)
266{
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000267 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400268 return 0;
269}
270
271static int fec_tx_task_disable(struct fec_priv *fec)
272{
273 return 0;
274}
275
276/**
277 * Initialize receive task's buffer descriptors
278 * @param[in] fec all we know about the device yet
279 * @param[in] count receive buffer count to be allocated
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000280 * @param[in] dsize desired size of each receive buffer
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400281 * @return 0 on success
282 *
Marek Vasut79e5f272013-10-12 20:36:25 +0200283 * Init all RX descriptors to default values.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400284 */
Marek Vasut79e5f272013-10-12 20:36:25 +0200285static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400286{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000287 uint32_t size;
Ye Lif24e4822018-01-10 13:20:44 +0800288 ulong data;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000289 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400290
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400291 /*
Marek Vasut79e5f272013-10-12 20:36:25 +0200292 * Reload the RX descriptors with default values and wipe
293 * the RX buffers.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400294 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000295 size = roundup(dsize, ARCH_DMA_MINALIGN);
296 for (i = 0; i < count; i++) {
Ye Lif24e4822018-01-10 13:20:44 +0800297 data = fec->rbd_base[i].data_pointer;
298 memset((void *)data, 0, dsize);
299 flush_dcache_range(data, data + size);
Marek Vasut79e5f272013-10-12 20:36:25 +0200300
301 fec->rbd_base[i].status = FEC_RBD_EMPTY;
302 fec->rbd_base[i].data_length = 0;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000303 }
304
305 /* Mark the last RBD to close the ring. */
Marek Vasut79e5f272013-10-12 20:36:25 +0200306 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400307 fec->rbd_index = 0;
308
Ye Lif24e4822018-01-10 13:20:44 +0800309 flush_dcache_range((ulong)fec->rbd_base,
310 (ulong)fec->rbd_base + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400311}
312
313/**
314 * Initialize transmit task's buffer descriptors
315 * @param[in] fec all we know about the device yet
316 *
317 * Transmit buffers are created externally. We only have to init the BDs here.\n
318 * Note: There is a race condition in the hardware. When only one BD is in
319 * use it must be marked with the WRAP bit to use it for every transmitt.
320 * This bit in combination with the READY bit results into double transmit
321 * of each data buffer. It seems the state machine checks READY earlier then
322 * resetting it after the first transfer.
323 * Using two BDs solves this issue.
324 */
325static void fec_tbd_init(struct fec_priv *fec)
326{
Ye Lif24e4822018-01-10 13:20:44 +0800327 ulong addr = (ulong)fec->tbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000328 unsigned size = roundup(2 * sizeof(struct fec_bd),
329 ARCH_DMA_MINALIGN);
Marek Vasut79e5f272013-10-12 20:36:25 +0200330
331 memset(fec->tbd_base, 0, size);
332 fec->tbd_base[0].status = 0;
333 fec->tbd_base[1].status = FEC_TBD_WRAP;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400334 fec->tbd_index = 0;
Marek Vasut79e5f272013-10-12 20:36:25 +0200335 flush_dcache_range(addr, addr + size);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400336}
337
338/**
339 * Mark the given read buffer descriptor as free
340 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
Jagan Teki567173a2016-12-06 00:00:50 +0100341 * @param[in] prbd buffer descriptor to mark free again
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400342 */
Jagan Teki567173a2016-12-06 00:00:50 +0100343static void fec_rbd_clean(int last, struct fec_bd *prbd)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400344{
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000345 unsigned short flags = FEC_RBD_EMPTY;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400346 if (last)
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000347 flags |= FEC_RBD_WRAP;
Jagan Teki567173a2016-12-06 00:00:50 +0100348 writew(flags, &prbd->status);
349 writew(0, &prbd->data_length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400350}
351
Jagan Tekif54183e2016-12-06 00:00:48 +0100352static int fec_get_hwaddr(int dev_id, unsigned char *mac)
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400353{
Fabio Estevambe252b62011-12-20 05:46:31 +0000354 imx_get_mac_from_fuse(dev_id, mac);
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500355 return !is_valid_ethaddr(mac);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400356}
357
Jagan Teki60752ca2016-12-06 00:00:49 +0100358#ifdef CONFIG_DM_ETH
359static int fecmxc_set_hwaddr(struct udevice *dev)
360#else
Stefano Babic4294b242010-02-01 14:51:30 +0100361static int fec_set_hwaddr(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100362#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400363{
Jagan Teki60752ca2016-12-06 00:00:49 +0100364#ifdef CONFIG_DM_ETH
365 struct fec_priv *fec = dev_get_priv(dev);
366 struct eth_pdata *pdata = dev_get_platdata(dev);
367 uchar *mac = pdata->enetaddr;
368#else
Stefano Babic4294b242010-02-01 14:51:30 +0100369 uchar *mac = dev->enetaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400370 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100371#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400372
373 writel(0, &fec->eth->iaddr1);
374 writel(0, &fec->eth->iaddr2);
375 writel(0, &fec->eth->gaddr1);
376 writel(0, &fec->eth->gaddr2);
377
Jagan Teki567173a2016-12-06 00:00:50 +0100378 /* Set physical address */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400379 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
Jagan Teki567173a2016-12-06 00:00:50 +0100380 &fec->eth->paddr1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400381 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
382
383 return 0;
384}
385
Jagan Teki567173a2016-12-06 00:00:50 +0100386/* Do initial configuration of the FEC registers */
Marek Vasuta5990b22012-05-01 11:09:41 +0000387static void fec_reg_setup(struct fec_priv *fec)
388{
389 uint32_t rcntrl;
390
Jagan Teki567173a2016-12-06 00:00:50 +0100391 /* Set interrupt mask register */
Marek Vasuta5990b22012-05-01 11:09:41 +0000392 writel(0x00000000, &fec->eth->imask);
393
Jagan Teki567173a2016-12-06 00:00:50 +0100394 /* Clear FEC-Lite interrupt event register(IEVENT) */
Marek Vasuta5990b22012-05-01 11:09:41 +0000395 writel(0xffffffff, &fec->eth->ievent);
396
Jagan Teki567173a2016-12-06 00:00:50 +0100397 /* Set FEC-Lite receive control register(R_CNTRL): */
Marek Vasuta5990b22012-05-01 11:09:41 +0000398
399 /* Start with frame length = 1518, common for all modes. */
400 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
benoit.thebaudeau@advans9d2d9242012-07-19 02:12:46 +0000401 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
402 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
403 if (fec->xcv_type == RGMII)
Marek Vasuta5990b22012-05-01 11:09:41 +0000404 rcntrl |= FEC_RCNTRL_RGMII;
405 else if (fec->xcv_type == RMII)
406 rcntrl |= FEC_RCNTRL_RMII;
Marek Vasuta5990b22012-05-01 11:09:41 +0000407
408 writel(rcntrl, &fec->eth->r_cntrl);
409}
410
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400411/**
412 * Start the FEC engine
413 * @param[in] dev Our device to handle
414 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100415#ifdef CONFIG_DM_ETH
416static int fec_open(struct udevice *dev)
417#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400418static int fec_open(struct eth_device *edev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100419#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400420{
Jagan Teki60752ca2016-12-06 00:00:49 +0100421#ifdef CONFIG_DM_ETH
422 struct fec_priv *fec = dev_get_priv(dev);
423#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400424 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100425#endif
Troy Kisky28774cb2012-02-07 14:08:46 +0000426 int speed;
Ye Lif24e4822018-01-10 13:20:44 +0800427 ulong addr, size;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000428 int i;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400429
430 debug("fec_open: fec_open(dev)\n");
431 /* full-duplex, heartbeat disabled */
432 writel(1 << 2, &fec->eth->x_cntrl);
433 fec->rbd_index = 0;
434
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000435 /* Invalidate all descriptors */
436 for (i = 0; i < FEC_RBD_NUM - 1; i++)
437 fec_rbd_clean(0, &fec->rbd_base[i]);
438 fec_rbd_clean(1, &fec->rbd_base[i]);
439
440 /* Flush the descriptors into RAM */
441 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
442 ARCH_DMA_MINALIGN);
Ye Lif24e4822018-01-10 13:20:44 +0800443 addr = (ulong)fec->rbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000444 flush_dcache_range(addr, addr + size);
445
Troy Kisky28774cb2012-02-07 14:08:46 +0000446#ifdef FEC_QUIRK_ENET_MAC
Jason Liu2ef2b952011-12-16 05:17:07 +0000447 /* Enable ENET HW endian SWAP */
448 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
Jagan Teki567173a2016-12-06 00:00:50 +0100449 &fec->eth->ecntrl);
Jason Liu2ef2b952011-12-16 05:17:07 +0000450 /* Enable ENET store and forward mode */
451 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
Jagan Teki567173a2016-12-06 00:00:50 +0100452 &fec->eth->x_wmrk);
Jason Liu2ef2b952011-12-16 05:17:07 +0000453#endif
Jagan Teki567173a2016-12-06 00:00:50 +0100454 /* Enable FEC-Lite controller */
John Rigbycb17b922010-01-25 23:12:55 -0700455 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
Jagan Teki567173a2016-12-06 00:00:50 +0100456 &fec->eth->ecntrl);
457
Fabio Estevam7df51fd2013-09-13 00:36:27 -0300458#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
John Rigby740d6ae2010-01-25 23:12:57 -0700459 udelay(100);
John Rigby740d6ae2010-01-25 23:12:57 -0700460
Jagan Teki567173a2016-12-06 00:00:50 +0100461 /* setup the MII gasket for RMII mode */
John Rigby740d6ae2010-01-25 23:12:57 -0700462 /* disable the gasket */
463 writew(0, &fec->eth->miigsk_enr);
464
465 /* wait for the gasket to be disabled */
466 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
467 udelay(2);
468
469 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
470 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
471
472 /* re-enable the gasket */
473 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
474
475 /* wait until MII gasket is ready */
476 int max_loops = 10;
477 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
478 if (--max_loops <= 0) {
479 printf("WAIT for MII Gasket ready timed out\n");
480 break;
481 }
482 }
483#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400484
Troy Kisky13947f42012-02-07 14:08:47 +0000485#ifdef CONFIG_PHYLIB
Troy Kisky4dc27ee2012-10-22 16:40:45 +0000486 {
Troy Kisky13947f42012-02-07 14:08:47 +0000487 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000488 int ret = phy_startup(fec->phydev);
489
490 if (ret) {
491 printf("Could not initialize PHY %s\n",
492 fec->phydev->dev->name);
493 return ret;
494 }
Troy Kisky13947f42012-02-07 14:08:47 +0000495 speed = fec->phydev->speed;
Troy Kisky13947f42012-02-07 14:08:47 +0000496 }
Hannes Schmelzer07507012016-06-22 12:07:14 +0200497#elif CONFIG_FEC_FIXED_SPEED
498 speed = CONFIG_FEC_FIXED_SPEED;
Troy Kisky13947f42012-02-07 14:08:47 +0000499#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400500 miiphy_wait_aneg(edev);
Troy Kisky28774cb2012-02-07 14:08:46 +0000501 speed = miiphy_speed(edev->name, fec->phy_id);
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200502 miiphy_duplex(edev->name, fec->phy_id);
Troy Kisky13947f42012-02-07 14:08:47 +0000503#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400504
Troy Kisky28774cb2012-02-07 14:08:46 +0000505#ifdef FEC_QUIRK_ENET_MAC
506 {
507 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
Alison Wangbcb6e902013-05-27 22:55:43 +0000508 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
Troy Kisky28774cb2012-02-07 14:08:46 +0000509 if (speed == _1000BASET)
510 ecr |= FEC_ECNTRL_SPEED;
511 else if (speed != _100BASET)
512 rcr |= FEC_RCNTRL_RMII_10T;
513 writel(ecr, &fec->eth->ecntrl);
514 writel(rcr, &fec->eth->r_cntrl);
515 }
516#endif
517 debug("%s:Speed=%i\n", __func__, speed);
518
Jagan Teki567173a2016-12-06 00:00:50 +0100519 /* Enable SmartDMA receive task */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400520 fec_rx_task_enable(fec);
521
522 udelay(100000);
523 return 0;
524}
525
Jagan Teki60752ca2016-12-06 00:00:49 +0100526#ifdef CONFIG_DM_ETH
527static int fecmxc_init(struct udevice *dev)
528#else
Jagan Teki567173a2016-12-06 00:00:50 +0100529static int fec_init(struct eth_device *dev, bd_t *bd)
Jagan Teki60752ca2016-12-06 00:00:49 +0100530#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400531{
Jagan Teki60752ca2016-12-06 00:00:49 +0100532#ifdef CONFIG_DM_ETH
533 struct fec_priv *fec = dev_get_priv(dev);
534#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400535 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100536#endif
Ye Lif24e4822018-01-10 13:20:44 +0800537 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
538 u8 *i;
539 ulong addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400540
John Rigbye9319f12010-10-13 14:31:08 -0600541 /* Initialize MAC address */
Jagan Teki60752ca2016-12-06 00:00:49 +0100542#ifdef CONFIG_DM_ETH
543 fecmxc_set_hwaddr(dev);
544#else
John Rigbye9319f12010-10-13 14:31:08 -0600545 fec_set_hwaddr(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +0100546#endif
John Rigbye9319f12010-10-13 14:31:08 -0600547
Jagan Teki567173a2016-12-06 00:00:50 +0100548 /* Setup transmit descriptors, there are two in total. */
Marek Vasut79e5f272013-10-12 20:36:25 +0200549 fec_tbd_init(fec);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400550
Marek Vasut79e5f272013-10-12 20:36:25 +0200551 /* Setup receive descriptors. */
552 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400553
Marek Vasuta5990b22012-05-01 11:09:41 +0000554 fec_reg_setup(fec);
Marek Vasut9eb37702011-09-11 18:05:31 +0000555
benoit.thebaudeau@advansf41471e2012-07-19 02:12:58 +0000556 if (fec->xcv_type != SEVENWIRE)
Troy Kisky575c5cc2012-10-22 16:40:41 +0000557 fec_mii_setspeed(fec->bus->priv);
Marek Vasut9eb37702011-09-11 18:05:31 +0000558
Jagan Teki567173a2016-12-06 00:00:50 +0100559 /* Set Opcode/Pause Duration Register */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400560 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
561 writel(0x2, &fec->eth->x_wmrk);
Jagan Teki567173a2016-12-06 00:00:50 +0100562
563 /* Set multicast address filter */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400564 writel(0x00000000, &fec->eth->gaddr1);
565 writel(0x00000000, &fec->eth->gaddr2);
566
Peng Fan238a53c2018-01-10 13:20:43 +0800567 /* Do not access reserved register */
568 if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
Peng Fanfbecbaa2015-08-12 17:46:51 +0800569 /* clear MIB RAM */
570 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
571 writel(0, i);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400572
Peng Fanfbecbaa2015-08-12 17:46:51 +0800573 /* FIFO receive start register */
574 writel(0x520, &fec->eth->r_fstart);
575 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400576
577 /* size and address of each buffer */
578 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
Ye Lif24e4822018-01-10 13:20:44 +0800579
580 addr = (ulong)fec->tbd_base;
581 writel((uint32_t)addr, &fec->eth->etdsr);
582
583 addr = (ulong)fec->rbd_base;
584 writel((uint32_t)addr, &fec->eth->erdsr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400585
Troy Kisky13947f42012-02-07 14:08:47 +0000586#ifndef CONFIG_PHYLIB
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400587 if (fec->xcv_type != SEVENWIRE)
588 miiphy_restart_aneg(dev);
Troy Kisky13947f42012-02-07 14:08:47 +0000589#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400590 fec_open(dev);
591 return 0;
592}
593
594/**
595 * Halt the FEC engine
596 * @param[in] dev Our device to handle
597 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100598#ifdef CONFIG_DM_ETH
599static void fecmxc_halt(struct udevice *dev)
600#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400601static void fec_halt(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100602#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400603{
Jagan Teki60752ca2016-12-06 00:00:49 +0100604#ifdef CONFIG_DM_ETH
605 struct fec_priv *fec = dev_get_priv(dev);
606#else
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200607 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100608#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400609 int counter = 0xffff;
610
Jagan Teki567173a2016-12-06 00:00:50 +0100611 /* issue graceful stop command to the FEC transmitter if necessary */
John Rigbycb17b922010-01-25 23:12:55 -0700612 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100613 &fec->eth->x_cntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400614
615 debug("eth_halt: wait for stop regs\n");
Jagan Teki567173a2016-12-06 00:00:50 +0100616 /* wait for graceful stop to register */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400617 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
John Rigbycb17b922010-01-25 23:12:55 -0700618 udelay(1);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400619
Jagan Teki567173a2016-12-06 00:00:50 +0100620 /* Disable SmartDMA tasks */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400621 fec_tx_task_disable(fec);
622 fec_rx_task_disable(fec);
623
624 /*
625 * Disable the Ethernet Controller
626 * Note: this will also reset the BD index counter!
627 */
John Rigby740d6ae2010-01-25 23:12:57 -0700628 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
Jagan Teki567173a2016-12-06 00:00:50 +0100629 &fec->eth->ecntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400630 fec->rbd_index = 0;
631 fec->tbd_index = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400632 debug("eth_halt: done\n");
633}
634
635/**
636 * Transmit one frame
637 * @param[in] dev Our ethernet device to handle
638 * @param[in] packet Pointer to the data to be transmitted
639 * @param[in] length Data count in bytes
640 * @return 0 on success
641 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100642#ifdef CONFIG_DM_ETH
643static int fecmxc_send(struct udevice *dev, void *packet, int length)
644#else
Joe Hershberger442dac42012-05-21 14:45:27 +0000645static int fec_send(struct eth_device *dev, void *packet, int length)
Jagan Teki60752ca2016-12-06 00:00:49 +0100646#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400647{
648 unsigned int status;
Ye Lif24e4822018-01-10 13:20:44 +0800649 u32 size;
650 ulong addr, end;
Marek Vasutbc1ce152012-08-29 03:49:49 +0000651 int timeout = FEC_XFER_TIMEOUT;
652 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400653
654 /*
655 * This routine transmits one frame. This routine only accepts
656 * 6-byte Ethernet addresses.
657 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100658#ifdef CONFIG_DM_ETH
659 struct fec_priv *fec = dev_get_priv(dev);
660#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400661 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100662#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400663
664 /*
665 * Check for valid length of data.
666 */
667 if ((length > 1500) || (length <= 0)) {
Stefano Babic4294b242010-02-01 14:51:30 +0100668 printf("Payload (%d) too large\n", length);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400669 return -1;
670 }
671
672 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000673 * Setup the transmit buffer. We are always using the first buffer for
674 * transmission, the second will be empty and only used to stop the DMA
675 * engine. We also flush the packet to RAM here to avoid cache trouble.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400676 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000677#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000678 swap_packet((uint32_t *)packet, length);
679#endif
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000680
Ye Lif24e4822018-01-10 13:20:44 +0800681 addr = (ulong)packet;
Marek Vasutefe24d22012-08-26 10:19:21 +0000682 end = roundup(addr + length, ARCH_DMA_MINALIGN);
683 addr &= ~(ARCH_DMA_MINALIGN - 1);
684 flush_dcache_range(addr, end);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000685
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400686 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
Ye Lif24e4822018-01-10 13:20:44 +0800687 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000688
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400689 /*
690 * update BD's status now
691 * This block:
692 * - is always the last in a chain (means no chain)
693 * - should transmitt the CRC
694 * - might be the last BD in the list, so the address counter should
695 * wrap (-> keep the WRAP flag)
696 */
697 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
698 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
699 writew(status, &fec->tbd_base[fec->tbd_index].status);
700
701 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000702 * Flush data cache. This code flushes both TX descriptors to RAM.
703 * After this code, the descriptors will be safely in RAM and we
704 * can start DMA.
705 */
706 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
Ye Lif24e4822018-01-10 13:20:44 +0800707 addr = (ulong)fec->tbd_base;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000708 flush_dcache_range(addr, addr + size);
709
710 /*
Marek Vasutab94cd42013-07-12 01:03:04 +0200711 * Below we read the DMA descriptor's last four bytes back from the
712 * DRAM. This is important in order to make sure that all WRITE
713 * operations on the bus that were triggered by previous cache FLUSH
714 * have completed.
715 *
716 * Otherwise, on MX28, it is possible to observe a corruption of the
717 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
718 * for the bus structure of MX28. The scenario is as follows:
719 *
720 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
721 * to DRAM due to flush_dcache_range()
722 * 2) ARM core writes the FEC registers via AHB_ARB2
723 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
724 *
725 * Note that 2) does sometimes finish before 1) due to reordering of
726 * WRITE accesses on the AHB bus, therefore triggering 3) before the
727 * DMA descriptor is fully written into DRAM. This results in occasional
728 * corruption of the DMA descriptor.
729 */
730 readl(addr + size - 4);
731
Jagan Teki567173a2016-12-06 00:00:50 +0100732 /* Enable SmartDMA transmit task */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400733 fec_tx_task_enable(fec);
734
735 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000736 * Wait until frame is sent. On each turn of the wait cycle, we must
737 * invalidate data cache to see what's really in RAM. Also, we need
738 * barrier here.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400739 */
Marek Vasut67449092012-08-29 03:49:50 +0000740 while (--timeout) {
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000741 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
Marek Vasutbc1ce152012-08-29 03:49:49 +0000742 break;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400743 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000744
Fabio Estevamf5992882014-08-25 13:34:17 -0300745 if (!timeout) {
746 ret = -EINVAL;
747 goto out;
748 }
749
750 /*
751 * The TDAR bit is cleared when the descriptors are all out from TX
752 * but on mx6solox we noticed that the READY bit is still not cleared
753 * right after TDAR.
754 * These are two distinct signals, and in IC simulation, we found that
755 * TDAR always gets cleared prior than the READY bit of last BD becomes
756 * cleared.
757 * In mx6solox, we use a later version of FEC IP. It looks like that
758 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
759 * version.
760 *
761 * Fix this by polling the READY bit of BD after the TDAR polling,
762 * which covers the mx6solox case and does not harm the other SoCs.
763 */
764 timeout = FEC_XFER_TIMEOUT;
765 while (--timeout) {
766 invalidate_dcache_range(addr, addr + size);
767 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
768 FEC_TBD_READY))
769 break;
770 }
771
Marek Vasut67449092012-08-29 03:49:50 +0000772 if (!timeout)
773 ret = -EINVAL;
774
Fabio Estevamf5992882014-08-25 13:34:17 -0300775out:
Marek Vasut67449092012-08-29 03:49:50 +0000776 debug("fec_send: status 0x%x index %d ret %i\n",
Jagan Teki567173a2016-12-06 00:00:50 +0100777 readw(&fec->tbd_base[fec->tbd_index].status),
778 fec->tbd_index, ret);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400779 /* for next transmission use the other buffer */
780 if (fec->tbd_index)
781 fec->tbd_index = 0;
782 else
783 fec->tbd_index = 1;
784
Marek Vasutbc1ce152012-08-29 03:49:49 +0000785 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400786}
787
788/**
789 * Pull one frame from the card
790 * @param[in] dev Our ethernet device to handle
791 * @return Length of packet read
792 */
Jagan Teki60752ca2016-12-06 00:00:49 +0100793#ifdef CONFIG_DM_ETH
794static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
795#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400796static int fec_recv(struct eth_device *dev)
Jagan Teki60752ca2016-12-06 00:00:49 +0100797#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400798{
Jagan Teki60752ca2016-12-06 00:00:49 +0100799#ifdef CONFIG_DM_ETH
800 struct fec_priv *fec = dev_get_priv(dev);
801#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400802 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki60752ca2016-12-06 00:00:49 +0100803#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400804 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
805 unsigned long ievent;
806 int frame_length, len = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400807 uint16_t bd_status;
Ye Lif24e4822018-01-10 13:20:44 +0800808 ulong addr, size, end;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000809 int i;
Ye Li07763ac2018-03-28 20:54:11 +0800810
811#ifdef CONFIG_DM_ETH
812 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
813 if (*packetp == 0) {
814 printf("%s: error allocating packetp\n", __func__);
815 return -ENOMEM;
816 }
817#else
Fabio Estevamfd37f192013-09-17 23:13:10 -0300818 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
Ye Li07763ac2018-03-28 20:54:11 +0800819#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400820
Jagan Teki567173a2016-12-06 00:00:50 +0100821 /* Check if any critical events have happened */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400822 ievent = readl(&fec->eth->ievent);
823 writel(ievent, &fec->eth->ievent);
Marek Vasuteda959f2011-10-24 23:40:03 +0000824 debug("fec_recv: ievent 0x%lx\n", ievent);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400825 if (ievent & FEC_IEVENT_BABR) {
Jagan Teki60752ca2016-12-06 00:00:49 +0100826#ifdef CONFIG_DM_ETH
827 fecmxc_halt(dev);
828 fecmxc_init(dev);
829#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400830 fec_halt(dev);
831 fec_init(dev, fec->bd);
Jagan Teki60752ca2016-12-06 00:00:49 +0100832#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400833 printf("some error: 0x%08lx\n", ievent);
834 return 0;
835 }
836 if (ievent & FEC_IEVENT_HBERR) {
837 /* Heartbeat error */
838 writel(0x00000001 | readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100839 &fec->eth->x_cntrl);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400840 }
841 if (ievent & FEC_IEVENT_GRA) {
842 /* Graceful stop complete */
843 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
Jagan Teki60752ca2016-12-06 00:00:49 +0100844#ifdef CONFIG_DM_ETH
845 fecmxc_halt(dev);
846#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400847 fec_halt(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +0100848#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400849 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
Jagan Teki567173a2016-12-06 00:00:50 +0100850 &fec->eth->x_cntrl);
Jagan Teki60752ca2016-12-06 00:00:49 +0100851#ifdef CONFIG_DM_ETH
852 fecmxc_init(dev);
853#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400854 fec_init(dev, fec->bd);
Jagan Teki60752ca2016-12-06 00:00:49 +0100855#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400856 }
857 }
858
859 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000860 * Read the buffer status. Before the status can be read, the data cache
861 * must be invalidated, because the data in RAM might have been changed
862 * by DMA. The descriptors are properly aligned to cachelines so there's
863 * no need to worry they'd overlap.
864 *
865 * WARNING: By invalidating the descriptor here, we also invalidate
866 * the descriptors surrounding this one. Therefore we can NOT change the
867 * contents of this descriptor nor the surrounding ones. The problem is
868 * that in order to mark the descriptor as processed, we need to change
869 * the descriptor. The solution is to mark the whole cache line when all
870 * descriptors in the cache line are processed.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400871 */
Ye Lif24e4822018-01-10 13:20:44 +0800872 addr = (ulong)rbd;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000873 addr &= ~(ARCH_DMA_MINALIGN - 1);
874 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
875 invalidate_dcache_range(addr, addr + size);
876
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400877 bd_status = readw(&rbd->status);
878 debug("fec_recv: status 0x%x\n", bd_status);
879
880 if (!(bd_status & FEC_RBD_EMPTY)) {
881 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
Jagan Teki567173a2016-12-06 00:00:50 +0100882 ((readw(&rbd->data_length) - 4) > 14)) {
883 /* Get buffer address and size */
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200884 addr = readl(&rbd->data_pointer);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400885 frame_length = readw(&rbd->data_length) - 4;
Jagan Teki567173a2016-12-06 00:00:50 +0100886 /* Invalidate data cache over the buffer */
Marek Vasutefe24d22012-08-26 10:19:21 +0000887 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
888 addr &= ~(ARCH_DMA_MINALIGN - 1);
889 invalidate_dcache_range(addr, end);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000890
Jagan Teki567173a2016-12-06 00:00:50 +0100891 /* Fill the buffer and pass it to upper layers */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000892#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200893 swap_packet((uint32_t *)addr, frame_length);
Marek Vasutbe7e87e2011-11-08 23:18:10 +0000894#endif
Ye Li07763ac2018-03-28 20:54:11 +0800895
896#ifdef CONFIG_DM_ETH
897 memcpy(*packetp, (char *)addr, frame_length);
898#else
Albert ARIBAUD \(3ADEV\)b1895842015-06-19 14:18:27 +0200899 memcpy(buff, (char *)addr, frame_length);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500900 net_process_received_packet(buff, frame_length);
Ye Li07763ac2018-03-28 20:54:11 +0800901#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400902 len = frame_length;
903 } else {
904 if (bd_status & FEC_RBD_ERR)
Ye Lif24e4822018-01-10 13:20:44 +0800905 debug("error frame: 0x%08lx 0x%08x\n",
906 addr, bd_status);
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400907 }
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000908
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400909 /*
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000910 * Free the current buffer, restart the engine and move forward
911 * to the next buffer. Here we check if the whole cacheline of
912 * descriptors was already processed and if so, we mark it free
913 * as whole.
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400914 */
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000915 size = RXDESC_PER_CACHELINE - 1;
916 if ((fec->rbd_index & size) == size) {
917 i = fec->rbd_index - size;
Ye Lif24e4822018-01-10 13:20:44 +0800918 addr = (ulong)&fec->rbd_base[i];
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000919 for (; i <= fec->rbd_index ; i++) {
920 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
921 &fec->rbd_base[i]);
922 }
923 flush_dcache_range(addr,
Jagan Teki567173a2016-12-06 00:00:50 +0100924 addr + ARCH_DMA_MINALIGN);
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000925 }
926
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400927 fec_rx_task_enable(fec);
928 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
929 }
930 debug("fec_recv: stop\n");
931
932 return len;
933}
934
Troy Kiskyef8e3a32012-10-22 16:40:44 +0000935static void fec_set_dev_name(char *dest, int dev_id)
936{
937 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
938}
939
Marek Vasut79e5f272013-10-12 20:36:25 +0200940static int fec_alloc_descs(struct fec_priv *fec)
941{
942 unsigned int size;
943 int i;
944 uint8_t *data;
Ye Lif24e4822018-01-10 13:20:44 +0800945 ulong addr;
Marek Vasut79e5f272013-10-12 20:36:25 +0200946
947 /* Allocate TX descriptors. */
948 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
949 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
950 if (!fec->tbd_base)
951 goto err_tx;
952
953 /* Allocate RX descriptors. */
954 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
955 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
956 if (!fec->rbd_base)
957 goto err_rx;
958
959 memset(fec->rbd_base, 0, size);
960
961 /* Allocate RX buffers. */
962
963 /* Maximum RX buffer size. */
Fabio Estevamdb5b7f52014-08-25 13:34:16 -0300964 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
Marek Vasut79e5f272013-10-12 20:36:25 +0200965 for (i = 0; i < FEC_RBD_NUM; i++) {
Fabio Estevamdb5b7f52014-08-25 13:34:16 -0300966 data = memalign(FEC_DMA_RX_MINALIGN, size);
Marek Vasut79e5f272013-10-12 20:36:25 +0200967 if (!data) {
968 printf("%s: error allocating rxbuf %d\n", __func__, i);
969 goto err_ring;
970 }
971
972 memset(data, 0, size);
973
Ye Lif24e4822018-01-10 13:20:44 +0800974 addr = (ulong)data;
975 fec->rbd_base[i].data_pointer = (uint32_t)addr;
Marek Vasut79e5f272013-10-12 20:36:25 +0200976 fec->rbd_base[i].status = FEC_RBD_EMPTY;
977 fec->rbd_base[i].data_length = 0;
978 /* Flush the buffer to memory. */
Ye Lif24e4822018-01-10 13:20:44 +0800979 flush_dcache_range(addr, addr + size);
Marek Vasut79e5f272013-10-12 20:36:25 +0200980 }
981
982 /* Mark the last RBD to close the ring. */
983 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
984
985 fec->rbd_index = 0;
986 fec->tbd_index = 0;
987
988 return 0;
989
990err_ring:
Ye Lif24e4822018-01-10 13:20:44 +0800991 for (; i >= 0; i--) {
992 addr = fec->rbd_base[i].data_pointer;
993 free((void *)addr);
994 }
Marek Vasut79e5f272013-10-12 20:36:25 +0200995 free(fec->rbd_base);
996err_rx:
997 free(fec->tbd_base);
998err_tx:
999 return -ENOMEM;
1000}
1001
1002static void fec_free_descs(struct fec_priv *fec)
1003{
1004 int i;
Ye Lif24e4822018-01-10 13:20:44 +08001005 ulong addr;
Marek Vasut79e5f272013-10-12 20:36:25 +02001006
Ye Lif24e4822018-01-10 13:20:44 +08001007 for (i = 0; i < FEC_RBD_NUM; i++) {
1008 addr = fec->rbd_base[i].data_pointer;
1009 free((void *)addr);
1010 }
Marek Vasut79e5f272013-10-12 20:36:25 +02001011 free(fec->rbd_base);
1012 free(fec->tbd_base);
1013}
1014
Peng Fan1bcabd72018-03-28 20:54:12 +08001015struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
Jagan Teki60752ca2016-12-06 00:00:49 +01001016{
Peng Fan1bcabd72018-03-28 20:54:12 +08001017 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
Jagan Teki60752ca2016-12-06 00:00:49 +01001018 struct mii_dev *bus;
1019 int ret;
1020
1021 bus = mdio_alloc();
1022 if (!bus) {
1023 printf("mdio_alloc failed\n");
1024 return NULL;
1025 }
1026 bus->read = fec_phy_read;
1027 bus->write = fec_phy_write;
1028 bus->priv = eth;
1029 fec_set_dev_name(bus->name, dev_id);
1030
1031 ret = mdio_register(bus);
1032 if (ret) {
1033 printf("mdio_register failed\n");
1034 free(bus);
1035 return NULL;
1036 }
1037 fec_mii_setspeed(eth);
1038 return bus;
1039}
1040
1041#ifndef CONFIG_DM_ETH
Troy Kiskyfe428b92012-10-22 16:40:46 +00001042#ifdef CONFIG_PHYLIB
1043int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1044 struct mii_dev *bus, struct phy_device *phydev)
1045#else
1046static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1047 struct mii_dev *bus, int phy_id)
1048#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001049{
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001050 struct eth_device *edev;
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001051 struct fec_priv *fec;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001052 unsigned char ethaddr[6];
Andy Duan979a5892017-04-10 19:44:35 +08001053 char mac[16];
Marek Vasute382fb42011-09-11 18:05:37 +00001054 uint32_t start;
1055 int ret = 0;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001056
1057 /* create and fill edev struct */
1058 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1059 if (!edev) {
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001060 puts("fec_mxc: not enough malloc memory for eth_device\n");
Marek Vasute382fb42011-09-11 18:05:37 +00001061 ret = -ENOMEM;
1062 goto err1;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001063 }
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001064
1065 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1066 if (!fec) {
1067 puts("fec_mxc: not enough malloc memory for fec_priv\n");
Marek Vasute382fb42011-09-11 18:05:37 +00001068 ret = -ENOMEM;
1069 goto err2;
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001070 }
1071
Nobuhiro Iwamatsude0b9572010-10-19 14:03:42 +09001072 memset(edev, 0, sizeof(*edev));
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001073 memset(fec, 0, sizeof(*fec));
1074
Marek Vasut79e5f272013-10-12 20:36:25 +02001075 ret = fec_alloc_descs(fec);
1076 if (ret)
1077 goto err3;
1078
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001079 edev->priv = fec;
1080 edev->init = fec_init;
1081 edev->send = fec_send;
1082 edev->recv = fec_recv;
1083 edev->halt = fec_halt;
Heiko Schocherfb57ec92010-04-27 07:43:52 +02001084 edev->write_hwaddr = fec_set_hwaddr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001085
Ye Lif24e4822018-01-10 13:20:44 +08001086 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001087 fec->bd = bd;
1088
Marek Vasut392b8502011-09-11 18:05:33 +00001089 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001090
1091 /* Reset chip. */
John Rigbycb17b922010-01-25 23:12:55 -07001092 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
Marek Vasute382fb42011-09-11 18:05:37 +00001093 start = get_timer(0);
1094 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1095 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
Vagrant Cascadian3450a852016-10-23 20:45:19 -07001096 printf("FEC MXC: Timeout resetting chip\n");
Marek Vasut79e5f272013-10-12 20:36:25 +02001097 goto err4;
Marek Vasute382fb42011-09-11 18:05:37 +00001098 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001099 udelay(10);
Marek Vasute382fb42011-09-11 18:05:37 +00001100 }
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001101
Marek Vasuta5990b22012-05-01 11:09:41 +00001102 fec_reg_setup(fec);
Troy Kiskyef8e3a32012-10-22 16:40:44 +00001103 fec_set_dev_name(edev->name, dev_id);
1104 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
Troy Kisky13947f42012-02-07 14:08:47 +00001105 fec->bus = bus;
Troy Kiskyfe428b92012-10-22 16:40:46 +00001106 fec_mii_setspeed(bus->priv);
1107#ifdef CONFIG_PHYLIB
1108 fec->phydev = phydev;
1109 phy_connect_dev(phydev, edev);
1110 /* Configure phy */
1111 phy_config(phydev);
1112#else
1113 fec->phy_id = phy_id;
1114#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001115 eth_register(edev);
Andy Duan979a5892017-04-10 19:44:35 +08001116 /* only support one eth device, the index number pointed by dev_id */
1117 edev->index = fec->dev_id;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001118
Andy Duanf01e4e12017-04-10 19:44:34 +08001119 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1120 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
Stefano Babic4294b242010-02-01 14:51:30 +01001121 memcpy(edev->enetaddr, ethaddr, 6);
Andy Duan979a5892017-04-10 19:44:35 +08001122 if (fec->dev_id)
1123 sprintf(mac, "eth%daddr", fec->dev_id);
1124 else
1125 strcpy(mac, "ethaddr");
Simon Glass00caae62017-08-03 12:22:12 -06001126 if (!env_get(mac))
Simon Glassfd1e9592017-08-03 12:22:11 -06001127 eth_env_set_enetaddr(mac, ethaddr);
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001128 }
Marek Vasute382fb42011-09-11 18:05:37 +00001129 return ret;
Marek Vasut79e5f272013-10-12 20:36:25 +02001130err4:
1131 fec_free_descs(fec);
Marek Vasute382fb42011-09-11 18:05:37 +00001132err3:
1133 free(fec);
1134err2:
1135 free(edev);
1136err1:
1137 return ret;
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001138}
1139
Troy Kiskyeef24482012-10-22 16:40:42 +00001140int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1141{
Troy Kiskyfe428b92012-10-22 16:40:46 +00001142 uint32_t base_mii;
1143 struct mii_dev *bus = NULL;
1144#ifdef CONFIG_PHYLIB
1145 struct phy_device *phydev = NULL;
1146#endif
1147 int ret;
1148
Peng Fanfbada482018-03-28 20:54:14 +08001149#ifdef CONFIG_FEC_MXC_MDIO_BASE
Troy Kiskyfe428b92012-10-22 16:40:46 +00001150 /*
1151 * The i.MX28 has two ethernet interfaces, but they are not equal.
1152 * Only the first one can access the MDIO bus.
1153 */
Peng Fanfbada482018-03-28 20:54:14 +08001154 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
Troy Kiskyfe428b92012-10-22 16:40:46 +00001155#else
1156 base_mii = addr;
1157#endif
Troy Kiskyeef24482012-10-22 16:40:42 +00001158 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001159 bus = fec_get_miibus(base_mii, dev_id);
1160 if (!bus)
1161 return -ENOMEM;
1162#ifdef CONFIG_PHYLIB
1163 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1164 if (!phydev) {
Måns Rullgård845a57b2015-12-08 15:38:46 +00001165 mdio_unregister(bus);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001166 free(bus);
1167 return -ENOMEM;
1168 }
1169 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1170#else
1171 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1172#endif
1173 if (ret) {
1174#ifdef CONFIG_PHYLIB
1175 free(phydev);
1176#endif
Måns Rullgård845a57b2015-12-08 15:38:46 +00001177 mdio_unregister(bus);
Troy Kiskyfe428b92012-10-22 16:40:46 +00001178 free(bus);
1179 }
1180 return ret;
Troy Kiskyeef24482012-10-22 16:40:42 +00001181}
1182
Troy Kisky09439c32012-10-22 16:40:40 +00001183#ifdef CONFIG_FEC_MXC_PHYADDR
Ilya Yanok0b23fb32009-07-21 19:32:21 +04001184int fecmxc_initialize(bd_t *bd)
1185{
Troy Kiskyeef24482012-10-22 16:40:42 +00001186 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1187 IMX_FEC_BASE);
Marek Vasut9e27e9d2011-09-16 01:13:47 +02001188}
1189#endif
1190
Troy Kisky13947f42012-02-07 14:08:47 +00001191#ifndef CONFIG_PHYLIB
Marek Vasut2e5f4422011-09-11 18:05:36 +00001192int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1193{
1194 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1195 fec->mii_postcall = cb;
1196 return 0;
1197}
Troy Kisky13947f42012-02-07 14:08:47 +00001198#endif
Jagan Teki60752ca2016-12-06 00:00:49 +01001199
1200#else
1201
Jagan Teki1ed25702016-12-06 00:00:51 +01001202static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1203{
1204 struct fec_priv *priv = dev_get_priv(dev);
1205 struct eth_pdata *pdata = dev_get_platdata(dev);
1206
1207 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1208}
1209
Ye Li07763ac2018-03-28 20:54:11 +08001210static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1211{
1212 if (packet)
1213 free(packet);
1214
1215 return 0;
1216}
1217
Jagan Teki60752ca2016-12-06 00:00:49 +01001218static const struct eth_ops fecmxc_ops = {
1219 .start = fecmxc_init,
1220 .send = fecmxc_send,
1221 .recv = fecmxc_recv,
Ye Li07763ac2018-03-28 20:54:11 +08001222 .free_pkt = fecmxc_free_pkt,
Jagan Teki60752ca2016-12-06 00:00:49 +01001223 .stop = fecmxc_halt,
1224 .write_hwaddr = fecmxc_set_hwaddr,
Jagan Teki1ed25702016-12-06 00:00:51 +01001225 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
Jagan Teki60752ca2016-12-06 00:00:49 +01001226};
1227
1228static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1229{
1230 struct phy_device *phydev;
1231 int mask = 0xffffffff;
1232
Lukasz Majewski178d4f02018-04-15 21:45:54 +02001233#ifdef CONFIG_FEC_MXC_PHYADDR
Jagan Teki60752ca2016-12-06 00:00:49 +01001234 mask = 1 << CONFIG_FEC_MXC_PHYADDR;
1235#endif
1236
1237 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
1238 if (!phydev)
1239 return -ENODEV;
1240
1241 phy_connect_dev(phydev, dev);
1242
1243 priv->phydev = phydev;
1244 phy_config(phydev);
1245
1246 return 0;
1247}
1248
1249static int fecmxc_probe(struct udevice *dev)
1250{
1251 struct eth_pdata *pdata = dev_get_platdata(dev);
1252 struct fec_priv *priv = dev_get_priv(dev);
1253 struct mii_dev *bus = NULL;
Jagan Teki60752ca2016-12-06 00:00:49 +01001254 uint32_t start;
1255 int ret;
1256
1257 ret = fec_alloc_descs(priv);
1258 if (ret)
1259 return ret;
1260
Jagan Teki60752ca2016-12-06 00:00:49 +01001261 /* Reset chip. */
Jagan Teki567173a2016-12-06 00:00:50 +01001262 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1263 &priv->eth->ecntrl);
Jagan Teki60752ca2016-12-06 00:00:49 +01001264 start = get_timer(0);
1265 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1266 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1267 printf("FEC MXC: Timeout reseting chip\n");
1268 goto err_timeout;
1269 }
1270 udelay(10);
1271 }
1272
1273 fec_reg_setup(priv);
Jagan Teki60752ca2016-12-06 00:00:49 +01001274
Peng Fan8b203862018-03-28 20:54:13 +08001275 priv->dev_id = dev->seq;
Peng Fanfbada482018-03-28 20:54:14 +08001276#ifdef CONFIG_FEC_MXC_MDIO_BASE
1277 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1278#else
Peng Fan8b203862018-03-28 20:54:13 +08001279 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
Peng Fanfbada482018-03-28 20:54:14 +08001280#endif
Lothar Waßmann306dd7d2017-06-27 15:23:16 +02001281 if (!bus) {
1282 ret = -ENOMEM;
1283 goto err_mii;
1284 }
1285
1286 priv->bus = bus;
1287 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1288 priv->interface = pdata->phy_interface;
1289 ret = fec_phy_init(priv, dev);
1290 if (ret)
1291 goto err_phy;
1292
Jagan Teki60752ca2016-12-06 00:00:49 +01001293 return 0;
1294
Jagan Teki60752ca2016-12-06 00:00:49 +01001295err_phy:
1296 mdio_unregister(bus);
1297 free(bus);
1298err_mii:
Ye Li2087eac2018-03-28 20:54:16 +08001299err_timeout:
Jagan Teki60752ca2016-12-06 00:00:49 +01001300 fec_free_descs(priv);
1301 return ret;
1302}
1303
1304static int fecmxc_remove(struct udevice *dev)
1305{
1306 struct fec_priv *priv = dev_get_priv(dev);
1307
1308 free(priv->phydev);
1309 fec_free_descs(priv);
1310 mdio_unregister(priv->bus);
1311 mdio_free(priv->bus);
1312
1313 return 0;
1314}
1315
1316static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1317{
1318 struct eth_pdata *pdata = dev_get_platdata(dev);
1319 struct fec_priv *priv = dev_get_priv(dev);
1320 const char *phy_mode;
1321
Simon Glassa821c4a2017-05-17 17:18:05 -06001322 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Jagan Teki60752ca2016-12-06 00:00:49 +01001323 priv->eth = (struct ethernet_regs *)pdata->iobase;
1324
1325 pdata->phy_interface = -1;
Simon Glasse160f7d2017-01-17 16:52:55 -07001326 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1327 NULL);
Jagan Teki60752ca2016-12-06 00:00:49 +01001328 if (phy_mode)
1329 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1330 if (pdata->phy_interface == -1) {
1331 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1332 return -EINVAL;
1333 }
1334
1335 /* TODO
1336 * Need to get the reset-gpio and related properties from DT
1337 * and implemet the enet reset code on .probe call
1338 */
1339
1340 return 0;
1341}
1342
1343static const struct udevice_id fecmxc_ids[] = {
1344 { .compatible = "fsl,imx6q-fec" },
Peng Fan979e0fc2018-03-28 20:54:15 +08001345 { .compatible = "fsl,imx6sl-fec" },
1346 { .compatible = "fsl,imx6sx-fec" },
1347 { .compatible = "fsl,imx6ul-fec" },
Lukasz Majewski948239e2018-04-15 21:54:22 +02001348 { .compatible = "fsl,imx53-fec" },
Jagan Teki60752ca2016-12-06 00:00:49 +01001349 { }
1350};
1351
1352U_BOOT_DRIVER(fecmxc_gem) = {
1353 .name = "fecmxc",
1354 .id = UCLASS_ETH,
1355 .of_match = fecmxc_ids,
1356 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1357 .probe = fecmxc_probe,
1358 .remove = fecmxc_remove,
1359 .ops = &fecmxc_ops,
1360 .priv_auto_alloc_size = sizeof(struct fec_priv),
1361 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1362};
1363#endif