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Michal Simekf7c8e492018-03-28 15:36:36 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h>
16
17/ {
18 model = "ZynqMP ZCU104 RevA";
19 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem3;
23 gpio0 = &gpio;
24 i2c0 = &i2c1;
25 mmc0 = &sdhci1;
26 rtc0 = &rtc;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &dcc;
30 spi0 = &qspi;
31 usb0 = &usb0;
32 };
33
34 chosen {
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
37 };
38
39 memory@0 {
40 device_type = "memory";
41 reg = <0x0 0x0 0x0 0x80000000>;
42 };
43};
44
45&can1 {
46 status = "okay";
47};
48
49&dcc {
50 status = "okay";
51};
52
53&gem3 {
54 status = "okay";
55 phy-handle = <&phy0>;
56 phy-mode = "rgmii-id";
57 phy0: phy@c {
58 reg = <0xc>;
59 ti,rx-internal-delay = <0x8>;
60 ti,tx-internal-delay = <0xa>;
61 ti,fifo-depth = <0x1>;
62 };
63};
64
65&gpio {
66 status = "okay";
67};
68
69&gpu {
70 status = "okay";
71};
72
73&i2c1 {
74 status = "okay";
75 clock-frequency = <400000>;
76
77 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
78 i2c-mux@74 { /* u34 */
79 compatible = "nxp,pca9548";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 reg = <0x74>;
83 i2c@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <0>;
87 /*
88 * IIC_EEPROM 1kB memory which uses 256B blocks
89 * where every block has different address.
90 * 0 - 256B address 0x54
91 * 256B - 512B address 0x55
92 * 512B - 768B address 0x56
93 * 768B - 1024B address 0x57
94 */
95 eeprom: eeprom@54 { /* u23 */
96 compatible = "atmel,24c08";
97 reg = <0x54>;
98 #address-cells = <1>;
99 #size-cells = <1>;
100 };
101 };
102
103 i2c@1 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <1>;
107 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
108 compatible = "idt,8t49n287";
109 reg = <0x6c>;
110 };
111 };
112
113 i2c@2 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 reg = <2>;
117 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
118 #clock-cells = <0>;
119 compatible = "infineon,irps5401";
120 reg = <0x43>;
121 };
122 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
123 #clock-cells = <0>;
124 compatible = "infineon,irps5401";
125 reg = <0x4d>;
126 };
127 };
128
129 i2c@4 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <4>;
Michal Simekce236dc2018-05-29 15:28:43 +0200133 tca6416_u97: gpio@20 {
Michal Simekf7c8e492018-03-28 15:36:36 +0200134 compatible = "ti,tca6416";
Michal Simekce236dc2018-05-29 15:28:43 +0200135 reg = <0x20>;
Michal Simekf7c8e492018-03-28 15:36:36 +0200136 gpio-controller;
137 #gpio-cells = <2>;
138 /*
139 * IRQ not connected
140 * Lines:
141 * 0 - IRPS5401_ALERT_B
142 * 1 - HDMI_8T49N241_INT_ALM
143 * 2 - MAX6643_OT_B
144 * 3 - MAX6643_FANFAIL_B
145 * 5 - IIC_MUX_RESET_B
146 * 6 - GEM3_EXP_RESET_B
147 * 7 - FMC_LPC_PRSNT_M2C_B
148 * 4, 10 - 17 - not connected
149 */
150 };
151 };
152
153 i2c@5 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 reg = <5>;
157 };
158
159 i2c@7 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 reg = <7>;
163 };
164
165 /* 3, 6 not connected */
166 };
167};
168
169&qspi {
170 status = "okay";
171 flash@0 {
Michal Simek0ed45f02018-07-26 12:43:42 +0200172 compatible = "m25p80", "spi-flash"; /* n25q512a 128MiB */
Michal Simekf7c8e492018-03-28 15:36:36 +0200173 #address-cells = <1>;
174 #size-cells = <1>;
175 reg = <0x0>;
176 spi-tx-bus-width = <1>;
177 spi-rx-bus-width = <4>;
178 spi-max-frequency = <108000000>; /* Based on DC1 spec */
179 partition@qspi-fsbl-uboot { /* for testing purpose */
180 label = "qspi-fsbl-uboot";
181 reg = <0x0 0x100000>;
182 };
183 partition@qspi-linux { /* for testing purpose */
184 label = "qspi-linux";
185 reg = <0x100000 0x500000>;
186 };
187 partition@qspi-device-tree { /* for testing purpose */
188 label = "qspi-device-tree";
189 reg = <0x600000 0x20000>;
190 };
191 partition@qspi-rootfs { /* for testing purpose */
192 label = "qspi-rootfs";
193 reg = <0x620000 0x5E0000>;
194 };
195 };
196};
197
198&rtc {
199 status = "okay";
200};
201
202&sata {
203 status = "okay";
204 /* SATA OOB timing settings */
205 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
206 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
207 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
208 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
209 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
210 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
211 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
212 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
213 phy-names = "sata-phy";
214 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
215};
216
217/* SD1 with level shifter */
218&sdhci1 {
219 status = "okay";
220 no-1-8-v;
221 xlnx,mio_bank = <1>;
222 disable-wp;
223};
224
225&serdes {
226 status = "okay";
227};
228
229&uart0 {
230 status = "okay";
231};
232
233&uart1 {
234 status = "okay";
235};
236
237/* ULPI SMSC USB3320 */
238&usb0 {
239 status = "okay";
240};
241
242&dwc3_0 {
243 status = "okay";
244 dr_mode = "host";
245 snps,usb3_lpm_capable;
246 phy-names = "usb3-phy";
247 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
248 maximum-speed = "super-speed";
249};
250
251&watchdog0 {
252 status = "okay";
253};
254
255&xilinx_ams {
256 status = "okay";
257};
258
259&ams_ps {
260 status = "okay";
261};
262
263&ams_pl {
264 status = "okay";
265};