| Wolfgang Denk | 86ea5f9 | 2006-02-22 00:43:16 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform |
| 3 | */ |
| 4 | |
| 5 | #define SDRAM_DDR 0 /* is SDR */ |
| 6 | |
| Wolfgang Denk | 86ea5f9 | 2006-02-22 00:43:16 +0100 | [diff] [blame] | 7 | /* Settings for XLB = 132 MHz */ |
| Wolfgang Denk | 86ea5f9 | 2006-02-22 00:43:16 +0100 | [diff] [blame] | 8 | |
| Wolfgang Denk | 86ea5f9 | 2006-02-22 00:43:16 +0100 | [diff] [blame] | 9 | #define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode RegisterMBAR + 0x0100 |
| 10 | #define SDRAM_CONTROL 0x504f0000 // Control RegisterMBAR + 0x0104 |
| 11 | #define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1MBAR + 0x0108 |
| 12 | #define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2MBAR + 0x010C |