Marcel Ziswiler | 0b42fdc | 2022-11-07 22:22:39 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ |
| 2 | /* |
| 3 | * Interconnect framework driver for i.MX SoC |
| 4 | * |
| 5 | * Copyright 2022 NXP |
| 6 | * Peng Fan <peng.fan@nxp.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H |
| 10 | #define __DT_BINDINGS_INTERCONNECT_IMX8MP_H |
| 11 | |
| 12 | #define IMX8MP_ICN_NOC 0 |
| 13 | #define IMX8MP_ICN_MAIN 1 |
| 14 | #define IMX8MP_ICS_DRAM 2 |
| 15 | #define IMX8MP_ICS_OCRAM 3 |
| 16 | #define IMX8MP_ICM_A53 4 |
| 17 | #define IMX8MP_ICM_SUPERMIX 5 |
| 18 | #define IMX8MP_ICM_GIC 6 |
| 19 | #define IMX8MP_ICM_MLMIX 7 |
| 20 | |
| 21 | #define IMX8MP_ICN_AUDIO 8 |
| 22 | #define IMX8MP_ICM_DSP 9 |
| 23 | #define IMX8MP_ICM_SDMA2PER 10 |
| 24 | #define IMX8MP_ICM_SDMA2BURST 11 |
| 25 | #define IMX8MP_ICM_SDMA3PER 12 |
| 26 | #define IMX8MP_ICM_SDMA3BURST 13 |
| 27 | #define IMX8MP_ICM_EDMA 14 |
| 28 | |
| 29 | #define IMX8MP_ICN_GPU 15 |
| 30 | #define IMX8MP_ICM_GPU2D 16 |
| 31 | #define IMX8MP_ICM_GPU3D 17 |
| 32 | |
| 33 | #define IMX8MP_ICN_HDMI 18 |
| 34 | #define IMX8MP_ICM_HRV 19 |
| 35 | #define IMX8MP_ICM_LCDIF_HDMI 20 |
| 36 | #define IMX8MP_ICM_HDCP 21 |
| 37 | |
| 38 | #define IMX8MP_ICN_HSIO 22 |
| 39 | #define IMX8MP_ICM_NOC_PCIE 23 |
| 40 | #define IMX8MP_ICM_USB1 24 |
| 41 | #define IMX8MP_ICM_USB2 25 |
| 42 | #define IMX8MP_ICM_PCIE 26 |
| 43 | |
| 44 | #define IMX8MP_ICN_MEDIA 27 |
| 45 | #define IMX8MP_ICM_LCDIF_RD 28 |
| 46 | #define IMX8MP_ICM_LCDIF_WR 29 |
| 47 | #define IMX8MP_ICM_ISI0 30 |
| 48 | #define IMX8MP_ICM_ISI1 31 |
| 49 | #define IMX8MP_ICM_ISI2 32 |
| 50 | #define IMX8MP_ICM_ISP0 33 |
| 51 | #define IMX8MP_ICM_ISP1 34 |
| 52 | #define IMX8MP_ICM_DWE 35 |
| 53 | |
| 54 | #define IMX8MP_ICN_VIDEO 36 |
| 55 | #define IMX8MP_ICM_VPU_G1 37 |
| 56 | #define IMX8MP_ICM_VPU_G2 38 |
| 57 | #define IMX8MP_ICM_VPU_H1 39 |
| 58 | |
| 59 | #endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */ |