| Simon Glass | 3a02f69 | 2019-12-08 17:40:08 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| Wolfgang Wallner | 7d53b5a | 2020-01-22 16:01:44 +0100 | [diff] [blame] | 3 | * Interrupt Timer Subsystem |
| 4 | * |
| Simon Glass | 3a02f69 | 2019-12-08 17:40:08 -0700 | [diff] [blame] | 5 | * Copyright (C) 2017 Intel Corporation. |
| 6 | * Copyright 2019 Google LLC |
| 7 | * |
| 8 | * Modified from coreboot itss.h |
| 9 | */ |
| 10 | |
| 11 | #ifndef _ASM_ARCH_ITSS_H |
| 12 | #define _ASM_ARCH_ITSS_H |
| 13 | |
| 14 | #define GPIO_IRQ_START 50 |
| 15 | #define GPIO_IRQ_END ITSS_MAX_IRQ |
| 16 | |
| 17 | #define ITSS_MAX_IRQ 119 |
| 18 | #define IRQS_PER_IPC 32 |
| 19 | #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC) |
| 20 | |
| 21 | /* Max PXRC registers in ITSS */ |
| 22 | #define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1) |
| 23 | |
| 24 | /* PIRQA Routing Control Register */ |
| 25 | #define PCR_ITSS_PIRQA_ROUT 0x3100 |
| 26 | /* PIRQB Routing Control Register */ |
| 27 | #define PCR_ITSS_PIRQB_ROUT 0x3101 |
| 28 | /* PIRQC Routing Control Register */ |
| 29 | #define PCR_ITSS_PIRQC_ROUT 0x3102 |
| 30 | /* PIRQD Routing Control Register */ |
| 31 | #define PCR_ITSS_PIRQD_ROUT 0x3103 |
| 32 | /* PIRQE Routing Control Register */ |
| 33 | #define PCR_ITSS_PIRQE_ROUT 0x3104 |
| 34 | /* PIRQF Routing Control Register */ |
| 35 | #define PCR_ITSS_PIRQF_ROUT 0x3105 |
| 36 | /* PIRQG Routing Control Register */ |
| 37 | #define PCR_ITSS_PIRQG_ROUT 0x3106 |
| 38 | /* PIRQH Routing Control Register */ |
| 39 | #define PCR_ITSS_PIRQH_ROUT 0x3107 |
| 40 | /* ITSS Interrupt polarity control */ |
| 41 | #define PCR_ITSS_IPC0_CONF 0x3200 |
| 42 | /* ITSS Power reduction control */ |
| 43 | #define PCR_ITSS_ITSSPRC 0x3300 |
| 44 | |
| 45 | #endif /* _ASM_ARCH_ITSS_H */ |