Khoronzhuk, Ivan | a43febd | 2014-10-22 17:18:21 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * TI serdes driver for keystone2. |
| 3 | * |
| 4 | * (C) Copyright 2014 |
| 5 | * Texas Instruments Incorporated, <www.ti.com> |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | |
| 12 | void ks2_serdes_sgmii_156p25mhz_setup(void) |
| 13 | { |
| 14 | unsigned int cnt; |
| 15 | |
| 16 | /* |
| 17 | * configure Serializer/Deserializer (SerDes) hardware. SerDes IP |
| 18 | * hardware vendor published only register addresses and their values |
| 19 | * to be used for configuring SerDes. So had to use hardcoded values |
| 20 | * below. |
| 21 | */ |
| 22 | clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000); |
| 23 | clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282); |
| 24 | clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438); |
| 25 | clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700); |
| 26 | clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000); |
| 27 | |
| 28 | clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080); |
| 29 | clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000); |
| 30 | clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000); |
| 31 | clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000); |
| 32 | clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8); |
| 33 | clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4); |
| 34 | clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400); |
| 35 | clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800); |
| 36 | clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082); |
| 37 | clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385); |
| 38 | |
| 39 | clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080); |
| 40 | clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000); |
| 41 | clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000); |
| 42 | clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000); |
| 43 | clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8); |
| 44 | clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4); |
| 45 | clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400); |
| 46 | clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800); |
| 47 | clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082); |
| 48 | clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385); |
| 49 | |
| 50 | clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080); |
| 51 | clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000); |
| 52 | clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000); |
| 53 | clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000); |
| 54 | clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8); |
| 55 | clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4); |
| 56 | clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400); |
| 57 | clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800); |
| 58 | clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082); |
| 59 | clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385); |
| 60 | |
| 61 | clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080); |
| 62 | clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000); |
| 63 | clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000); |
| 64 | clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000); |
| 65 | clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8); |
| 66 | clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4); |
| 67 | clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400); |
| 68 | clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800); |
| 69 | clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082); |
| 70 | clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385); |
| 71 | |
| 72 | clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800); |
| 73 | clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000); |
| 74 | clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00); |
| 75 | clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600); |
| 76 | clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000); |
| 77 | clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000); |
| 78 | clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000); |
| 79 | clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b); |
| 80 | clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000); |
| 81 | clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e); |
| 82 | clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003); |
| 83 | clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f); |
| 84 | |
| 85 | clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00); |
| 86 | clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72); |
| 87 | clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100); |
| 88 | clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060); |
| 89 | clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000); |
| 90 | clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220); |
| 91 | clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602); |
| 92 | clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1); |
| 93 | clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989); |
| 94 | clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001); |
| 95 | clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000); |
| 96 | clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000); |
| 97 | clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d); |
| 98 | |
| 99 | /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/ |
| 100 | clrbits_le32(0x0232a010, 1 << 28); |
| 101 | |
| 102 | /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */ |
| 103 | clrbits_le32(0x0232a228, 1 << 29); |
| 104 | writel(0xF800F8C0, 0x0232bfe0); |
| 105 | clrbits_le32(0x0232a428, 1 << 29); |
| 106 | writel(0xF800F8C0, 0x0232bfe4); |
| 107 | clrbits_le32(0x0232a628, 1 << 29); |
| 108 | writel(0xF800F8C0, 0x0232bfe8); |
| 109 | clrbits_le32(0x0232a828, 1 << 29); |
| 110 | writel(0xF800F8C0, 0x0232bfec); |
| 111 | |
| 112 | /*Enable pll via the pll_ctrl 0x0014*/ |
| 113 | writel(0xe0000000, 0x0232bff4) |
| 114 | ; |
| 115 | |
| 116 | /*Waiting for SGMII Serdes PLL lock.*/ |
| 117 | for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--) |
| 118 | ; |
| 119 | for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--) |
| 120 | ; |
| 121 | for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--) |
| 122 | ; |
| 123 | for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--) |
| 124 | ; |
| 125 | |
| 126 | udelay(45000); |
| 127 | } |