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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific,
26 * for SinoVee Microsystems SC8xx series SBC
27 * http://www.fel.com.cn (Chinese)
28 * http://www.sinovee.com (English)
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/* Custom configuration */
35/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
36/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
37/*#define CONFIG_FEL8xx_AT */
38/*#define CONFIG_LCD */
39/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
40/* #define CONFIG_50MHz */
41/* #define CONFIG_66MHz */
42/* #define CONFIG_75MHz */
43#define CONFIG_80MHz
44/*#define CONFIG_100MHz */
45/* #define CONFIG_BUS_DIV2 1 */
46/* for BOOT device port size */
47/* #define CONFIG_BOOT_8B */
48#define CONFIG_BOOT_16B
49/* #define CONFIG_BOOT_32B */
50/* #define CONFIG_CAN_DRIVER */
51/* #define DEBUG */
52#define CONFIG_FEC_ENET
53
54/* #define CONFIG_SDRAM_16M */
55#define CONFIG_SDRAM_32M
56/* #define CONFIG_SDRAM_64M */
57#define CFG_RESET_ADDRESS 0xffffffff
58/*
59 * High Level Configuration Options
60 * (easy to change)
61 */
62
63/* #define CONFIG_MPC823 1 */
64/* #define CONFIG_MPC850 1 */
65#define CONFIG_MPC855 1
66/* #define CONFIG_MPC860 1 */
67/* #define CONFIG_MPC860T 1 */
68
69#undef CONFIG_WATCHDOG /* watchdog */
70
71#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
72
73#ifdef CONFIG_LCD /* with LCD controller ? */
wdenkfd3103b2003-11-25 16:55:19 +000074/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
wdenkdc7c9a12003-03-26 06:55:25 +000075#endif
76
77#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
78#undef CONFIG_8xx_CONS_SMC2
79#undef CONFIG_8xx_CONS_NONE
80#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */
81#if 0
82#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
83#else
84#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
85#endif
86
87#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
88
89#define CONFIG_BOARD_TYPES 1 /* support board types */
90
91#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
92
93#undef CONFIG_BOOTARGS
94#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk8bde7f72003-06-27 21:31:46 +000095 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010096 "nfsroot=${serverip}:${rootpath}\0" \
wdenk8bde7f72003-06-27 21:31:46 +000097 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010098 "addip=setenv bootargs ${bootargs} " \
99 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
100 ":${hostname}:${netdev}:off panic=1\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000101 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100102 "bootm ${kernel_addr}\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000103 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100104 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
105 "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000106 "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
107 "bootfile=pImage-sc855t\0" \
108 "kernel_addr=48000000\0" \
109 "ramdisk_addr=48100000\0" \
110 ""
wdenkdc7c9a12003-03-26 06:55:25 +0000111#define CONFIG_BOOTCOMMAND \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100112 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
113 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkdc7c9a12003-03-26 06:55:25 +0000114 "tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
115
116#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
117#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
118
119
120#ifdef CONFIG_LCD
121# undef CONFIG_STATUS_LED /* disturbs display */
122#else
123# define CONFIG_STATUS_LED 1 /* Status LED enabled */
124#endif /* CONFIG_LCD */
125
126#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
127
128#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
129
130#define CONFIG_MAC_PARTITION
131#define CONFIG_DOS_PARTITION
132
133#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
134
135#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk8bde7f72003-06-27 21:31:46 +0000136 CFG_CMD_ASKENV | \
137 CFG_CMD_DHCP | \
wdenkdc7c9a12003-03-26 06:55:25 +0000138 CFG_CMD_DOC | \
139/* CFG_CMD_IDE |*/ \
140 CFG_CMD_DATE )
141
142/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
143#include <cmd_confdefs.h>
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100144#define CFG_NAND_LEGACY
wdenkdc7c9a12003-03-26 06:55:25 +0000145
146/*
147 * Miscellaneous configurable options
148 */
149#define CFG_LONGHELP /* undef to save memory */
150#define CFG_PROMPT "=> " /* Monitor Command Prompt */
151
152#ifdef CFG_HUSH_PARSER
153#define CFG_PROMPT_HUSH_PS2 "> "
154#endif
155
156#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
157#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
158#else
159#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
160#endif
161#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
162#define CFG_MAXARGS 16 /* max number of command args */
163#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
164
165#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
166#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
167
168#define CFG_LOAD_ADDR 0x100000 /* default load address */
169
170#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
171
172#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
173
174/*
175 * Low Level Configuration Settings
176 * (address mappings, register initial values, etc.)
177 * You should know what you are doing if you make changes here.
178 */
179/*-----------------------------------------------------------------------
180 * Internal Memory Mapped Register
181 */
182#define CFG_IMMR 0xFF000000
183
184/*-----------------------------------------------------------------------
185 * Definitions for initial stack pointer and data area (in DPRAM)
186 */
187#define CFG_INIT_RAM_ADDR CFG_IMMR
188#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
189#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
190#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
191#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
192
193/*-----------------------------------------------------------------------
194 * Start addresses for the final memory configuration
195 * (Set up by the startup code)
196 * Please note that CFG_SDRAM_BASE _must_ start at 0
197 */
198#define CFG_SDRAM_BASE 0x00000000
199#define CFG_FLASH_BASE 0x40000000
200#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
201#define CFG_MONITOR_BASE CFG_FLASH_BASE
202#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
203
204/*
205 * For booting Linux, the board info and command line data
206 * have to be in the first 8 MB of memory, since this is
207 * the maximum mapped by the Linux kernel during initialization.
208 */
209#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
210
211/*-----------------------------------------------------------------------
212 * FLASH organization
213 */
214#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
215#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
216
217#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
218#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
219
220#define CFG_ENV_IS_IN_FLASH 1
221
222#ifdef CONFIG_BOOT_8B
223#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
224#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
225#elif defined (CONFIG_BOOT_16B)
226#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
227#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
228#elif defined (CONFIG_BOOT_32B)
229#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
230#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
231#endif
232
233/* Address and size of Redundant Environment Sector */
234#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
235#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
236
237
238/*-----------------------------------------------------------------------
239 * Hardware Information Block
240 */
241#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
242#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
243#define CFG_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */
244
245/*-----------------------------------------------------------------------
246 * Cache Configuration
247 */
248#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
249#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
250#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
251#endif
252
253/*-----------------------------------------------------------------------
254 * SYPCR - System Protection Control 11-9
255 * SYPCR can only be written once after reset!
256 *-----------------------------------------------------------------------
257 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
258 */
259#if defined(CONFIG_WATCHDOG)
260/*#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
261 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
262*/
263#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
264 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
265#else
266#define CFG_SYPCR 0xffffff88
267#endif
268
269/*-----------------------------------------------------------------------
270 * SIUMCR - SIU Module Configuration 11-6
271 *-----------------------------------------------------------------------
272 * PCMCIA config., multi-function pin tri-state
273 */
274#ifndef CONFIG_CAN_DRIVER
275/*#define CFG_SIUMCR 0x00610c00 */
wdenk8bde7f72003-06-27 21:31:46 +0000276#define CFG_SIUMCR 0x00000000
wdenkdc7c9a12003-03-26 06:55:25 +0000277#else /* we must activate GPL5 in the SIUMCR for CAN */
278#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
279#endif /* CONFIG_CAN_DRIVER */
280
281/*-----------------------------------------------------------------------
282 * TBSCR - Time Base Status and Control 11-26
283 *-----------------------------------------------------------------------
284 * Clear Reference Interrupt Status, Timebase freezing enabled
285 */
286#define CFG_TBSCR 0x0001
287
288/*-----------------------------------------------------------------------
289 * RTCSC - Real-Time Clock Status and Control Register 11-27
290 *-----------------------------------------------------------------------
291 */
292#define CFG_RTCSC 0x00c3
293
294/*-----------------------------------------------------------------------
295 * PISCR - Periodic Interrupt Status and Control 11-31
296 *-----------------------------------------------------------------------
297 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
298 */
299#define CFG_PISCR 0x0000
300
301/*-----------------------------------------------------------------------
302 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
303 *-----------------------------------------------------------------------
304 * Reset PLL lock status sticky bit, timer expired status bit and timer
305 * interrupt status bit
306 */
307#if defined (CONFIG_100MHz)
308#define CFG_PLPRCR 0x06301000
309#define CONFIG_8xx_GCLK_FREQ 100000000
310#elif defined (CONFIG_80MHz)
311#define CFG_PLPRCR 0x04f01000
312#define CONFIG_8xx_GCLK_FREQ 80000000
wdenk8bde7f72003-06-27 21:31:46 +0000313#elif defined(CONFIG_75MHz)
314#define CFG_PLPRCR 0x04a00100
wdenkdc7c9a12003-03-26 06:55:25 +0000315#define CONFIG_8xx_GCLK_FREQ 75000000
wdenk8bde7f72003-06-27 21:31:46 +0000316#elif defined(CONFIG_66MHz)
317#define CFG_PLPRCR 0x04101000
wdenkdc7c9a12003-03-26 06:55:25 +0000318#define CONFIG_8xx_GCLK_FREQ 66000000
wdenk8bde7f72003-06-27 21:31:46 +0000319#elif defined(CONFIG_50MHz)
320#define CFG_PLPRCR 0x03101000
wdenkdc7c9a12003-03-26 06:55:25 +0000321#define CONFIG_8xx_GCLK_FREQ 50000000
wdenk8bde7f72003-06-27 21:31:46 +0000322#endif
wdenkdc7c9a12003-03-26 06:55:25 +0000323
324/*-----------------------------------------------------------------------
325 * SCCR - System Clock and reset Control Register 15-27
326 *-----------------------------------------------------------------------
327 * Set clock output, timebase and RTC source and divider,
328 * power management and some other internal clocks
329 */
330#define SCCR_MASK SCCR_EBDF11
wdenk8bde7f72003-06-27 21:31:46 +0000331#ifdef CONFIG_BUS_DIV2
wdenkdc7c9a12003-03-26 06:55:25 +0000332#define CFG_SCCR 0x02020000 | SCCR_RTSEL
333#else /* up to 50 MHz we use a 1:1 clock */
334#define CFG_SCCR 0x02000000 | SCCR_RTSEL
wdenk8bde7f72003-06-27 21:31:46 +0000335#endif
wdenkdc7c9a12003-03-26 06:55:25 +0000336
337/*-----------------------------------------------------------------------
338 * PCMCIA stuff
339 *-----------------------------------------------------------------------
340 *
341 */
342#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
343#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
344#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
345#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
346#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
347#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
348#define CFG_PCMCIA_IO_ADDR (0xEC000000)
349#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
350
351/*-----------------------------------------------------------------------
352 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
353 *-----------------------------------------------------------------------
354 */
355
356#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
357
358#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
359#undef CONFIG_IDE_LED /* LED for ide not supported */
360#undef CONFIG_IDE_RESET /* reset for ide not supported */
361
362#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
363#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
364
365#define CFG_ATA_BASE_ADDR 0xFE100010
366#define CFG_ATA_IDE0_OFFSET 0x0000
367/*#define CFG_ATA_IDE1_OFFSET 0x0C00 */
368#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O
369 */
370#define CFG_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses
371 */
372#define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers
373 */
wdenk8bde7f72003-06-27 21:31:46 +0000374#define CONFIG_ATAPI
wdenkdc7c9a12003-03-26 06:55:25 +0000375#define CFG_PIO_MODE 0
376
377/*-----------------------------------------------------------------------
378 *
379 *-----------------------------------------------------------------------
380 *
381 */
382/*#define CFG_DER 0x2002000F*/
383#define CFG_DER 0x0
384
385/*
386 * Init Memory Controller:
387 *
388 * BR0/1 and OR0/1 (FLASH)
389 */
390
391#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
392#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
393
394/* used to re-map FLASH both when starting from SRAM or FLASH:
395 * restrict access enough to keep SRAM working (if any)
396 * but not too much to meddle with FLASH accesses
397 */
398#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
399#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
400
401/*
402 * FLASH timing:
403 */
wdenk8bde7f72003-06-27 21:31:46 +0000404#if defined(CONFIG_100MHz)
405#define CFG_OR_TIMING_FLASH 0x000002f4
406#define CFG_OR_TIMING_DOC 0x000002f4
wdenkdc7c9a12003-03-26 06:55:25 +0000407#define CFG_MxMR_PTx 0x61000000
408#define CFG_MPTPR 0x400
409
410#elif defined(CONFIG_80MHz)
wdenk8bde7f72003-06-27 21:31:46 +0000411#define CFG_OR_TIMING_FLASH 0x00000ff4
412#define CFG_OR_TIMING_DOC 0x000001f4
wdenkdc7c9a12003-03-26 06:55:25 +0000413#define CFG_MxMR_PTx 0x4e000000
414#define CFG_MPTPR 0x400
415
wdenk8bde7f72003-06-27 21:31:46 +0000416#elif defined(CONFIG_75MHz)
417#define CFG_OR_TIMING_FLASH 0x000008f4
418#define CFG_OR_TIMING_DOC 0x000002f4
wdenkdc7c9a12003-03-26 06:55:25 +0000419#define CFG_MxMR_PTx 0x49000000
420#define CFG_MPTPR 0x400
421
422#elif defined(CONFIG_66MHz)
423#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk8bde7f72003-06-27 21:31:46 +0000424 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkdc7c9a12003-03-26 06:55:25 +0000425/*#define CFG_OR_TIMING_FLASH 0x000001f4 */
wdenk8bde7f72003-06-27 21:31:46 +0000426#define CFG_OR_TIMING_DOC 0x000003f4
wdenkdc7c9a12003-03-26 06:55:25 +0000427#define CFG_MxMR_PTx 0x40000000
428#define CFG_MPTPR 0x400
429
430#else /* 50 MHz */
431#define CFG_OR_TIMING_FLASH 0x00000ff4
wdenk8bde7f72003-06-27 21:31:46 +0000432#define CFG_OR_TIMING_DOC 0x000001f4
wdenkdc7c9a12003-03-26 06:55:25 +0000433#define CFG_MxMR_PTx 0x30000000
434#define CFG_MPTPR 0x400
435#endif /*CONFIG_??MHz */
436
437
438#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */
439#define CFG_OR0_PRELIM (0xffe00000 | CFG_OR_TIMING_FLASH)
440#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
441#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */
442#define CFG_OR0_PRELIM (0xffc00000 | CFG_OR_TIMING_FLASH)
443#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
444#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
445#define CFG_OR0_PRELIM (0xfc000000 | CFG_OR_TIMING_FLASH)
446#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
447#else
448#error Boot device port size missing.
449#endif
450
451/*
452 * Disk-On-Chip configuration
453 */
454
455#define CFG_DOC_SHORT_TIMEOUT
456#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
457
458#define CFG_DOC_SUPPORT_2000
459#define CFG_DOC_SUPPORT_MILLENNIUM
460#define CFG_DOC_BASE 0x80000000
461
462
463/*
464 * Internal Definitions
465 *
466 * Boot Flags
467 */
468#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
469#define BOOTFLAG_WARM 0x02 /* Software reboot */
470
471#endif /* __CONFIG_H */