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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / fa140172cb6e98ee8a820289e5106cbfbdcc79c3 / . / arch / arm / dts / imx8mm-u-boot.dtsi
blob: 035282bf0b0029d478db8bf2c6c15d592dc717a9 [file] [log] [blame]
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Jagan Teki <jagan@amarulasolutions.com>
4 */
5
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]6/ {
7 binman: binman {
8 multiple-images;
9 };
10};
11
Marcel Ziswilerdbd5ca22022-11-07 22:22:41 +0100[diff] [blame]12&soc {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]13 bootph-all;
14 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]15};
16
17&aips1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]18 bootph-all;
19 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]20};
21
22&aips2 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]23 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]24};
25
26&aips3 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]28};
29
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]30&binman {
31 u-boot-spl-ddr {
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]32 align = <4>;
33 align-size = <4>;
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]34 filename = "u-boot-spl-ddr.bin";
35 pad-byte = <0xff>;
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]36
37 u-boot-spl {
38 align-end = <4>;
Marcel Ziswiler86b7f202021-10-23 01:15:15 +0200[diff] [blame]39 filename = "u-boot-spl.bin";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]40 };
41
Peng Fan25daa2c2022-07-26 16:41:20 +0800[diff] [blame]42 ddr-1d-imem-fw {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]43 filename = "lpddr4_pmu_train_1d_imem.bin";
Peng Fanc065a6c2022-07-26 16:41:22 +0800[diff] [blame]44 align-end = <4>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]45 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]46 };
47
Peng Fan25daa2c2022-07-26 16:41:20 +0800[diff] [blame]48 ddr-1d-dmem-fw {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]49 filename = "lpddr4_pmu_train_1d_dmem.bin";
Peng Fanc065a6c2022-07-26 16:41:22 +0800[diff] [blame]50 align-end = <4>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]51 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]52 };
53
Peng Fan25daa2c2022-07-26 16:41:20 +0800[diff] [blame]54 ddr-2d-imem-fw {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]55 filename = "lpddr4_pmu_train_2d_imem.bin";
Peng Fanc065a6c2022-07-26 16:41:22 +0800[diff] [blame]56 align-end = <4>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]57 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]58 };
59
Peng Fan25daa2c2022-07-26 16:41:20 +0800[diff] [blame]60 ddr-2d-dmem-fw {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]61 filename = "lpddr4_pmu_train_2d_dmem.bin";
Peng Fanc065a6c2022-07-26 16:41:22 +0800[diff] [blame]62 align-end = <4>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]63 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]64 };
65 };
66
67 spl {
68 filename = "spl.bin";
69
70 mkimage {
71 args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
72
73 blob {
74 filename = "u-boot-spl-ddr.bin";
75 };
76 };
77 };
78
79 itb {
80 filename = "u-boot.itb";
81
82 fit {
83 description = "Configuration to load ATF before U-Boot";
Marek Vasut6039e0e2023-05-28 23:00:30 +0200[diff] [blame]84#ifndef CONFIG_IMX_HAB
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]85 fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
Marek Vasut6039e0e2023-05-28 23:00:30 +0200[diff] [blame]86#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]87 fit,fdt-list = "of-list";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]88 #address-cells = <1>;
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]89
90 images {
91 uboot {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]92 arch = "arm64";
93 compression = "none";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]94 description = "U-Boot (64-bit)";
Simon Glass98463902022-10-20 18:22:39 -0600[diff] [blame]95 load = <CONFIG_TEXT_BASE>;
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]96 type = "standalone";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]97
Patrick Wildt49f55652022-01-13 15:22:17 +0100[diff] [blame]98 uboot-blob {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]99 filename = "u-boot-nodtb.bin";
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]100 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]101 };
102 };
103
Marek Vasut9694c0532022-12-22 01:46:37 +0100[diff] [blame]104#ifndef CONFIG_ARMV8_PSCI
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]105 atf {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]106 arch = "arm64";
107 compression = "none";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]108 description = "ARM Trusted Firmware";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]109 entry = <0x920000>;
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]110 load = <0x920000>;
111 type = "firmware";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]112
Patrick Wildt49f55652022-01-13 15:22:17 +0100[diff] [blame]113 atf-blob {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]114 filename = "bl31.bin";
Marcel Ziswiler310de882022-04-08 10:06:56 +0200[diff] [blame]115 type = "atf-bl31";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]116 };
117 };
Marek Vasut9694c0532022-12-22 01:46:37 +0100[diff] [blame]118#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]119
120 binman_fip: fip {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]121 arch = "arm64";
122 compression = "none";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]123 description = "Trusted Firmware FIP";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]124 load = <0x40310000>;
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]125 type = "firmware";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]126 };
127
128 @fdt-SEQ {
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]129 compression = "none";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]130 description = "NAME";
131 type = "flat_dt";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]132
Patrick Wildt49f55652022-01-13 15:22:17 +0100[diff] [blame]133 uboot-fdt-blob {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]134 filename = "u-boot.dtb";
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]135 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]136 };
137 };
138 };
139
140 configurations {
141 default = "@config-DEFAULT-SEQ";
142
143 binman_configuration: @config-SEQ {
144 description = "NAME";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]145 fdt = "fdt-SEQ";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]146 firmware = "uboot";
Marek Vasut9694c0532022-12-22 01:46:37 +0100[diff] [blame]147#ifndef CONFIG_ARMV8_PSCI
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]148 loadables = "atf";
Marek Vasut9694c0532022-12-22 01:46:37 +0100[diff] [blame]149#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]150 };
151 };
152 };
153 };
154
155 imx-boot {
156 filename = "flash.bin";
157 pad-byte = <0x00>;
158
Mamta Shuklade997212022-07-12 14:36:18 +0000[diff] [blame]159#ifdef CONFIG_FSPI_CONF_HEADER
160 fspi_conf_block {
161 filename = CONFIG_FSPI_CONF_FILE;
162 type = "blob-ext";
163 size = <0x1000>;
164 };
165
166 spl {
167 filename = "spl.bin";
168 offset = <0x1000>;
169 type = "blob-ext";
170 };
171
172 binman_uboot: uboot {
173 filename = "u-boot.itb";
174 offset = <0x58C00>;
175 type = "blob-ext";
176 };
177#else
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]178 spl {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]179 filename = "spl.bin";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]180 offset = <0x0>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]181 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]182 };
183
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]184 binman_uboot: uboot {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]185 filename = "u-boot.itb";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200[diff] [blame]186 offset = <0x57c00>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200[diff] [blame]187 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]188 };
Mamta Shuklade997212022-07-12 14:36:18 +0000[diff] [blame]189#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200[diff] [blame]190 };
191};
192
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]193&clk {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]194 bootph-all;
195 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]196 /delete-property/ assigned-clocks;
197 /delete-property/ assigned-clock-parents;
198 /delete-property/ assigned-clock-rates;
199};
200
201&iomuxc {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]202 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]203};
204
205&osc_24m {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]206 bootph-all;
207 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530[diff] [blame]208};
Marcel Ziswiler24a7a3c2022-07-21 15:27:40 +0200[diff] [blame]209
210&spba1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]211 bootph-all;
212 bootph-pre-ram;
Marcel Ziswiler24a7a3c2022-07-21 15:27:40 +0200[diff] [blame]213};
214
215&spba2 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]216 bootph-all;
217 bootph-pre-ram;
Marcel Ziswiler24a7a3c2022-07-21 15:27:40 +0200[diff] [blame]218};