blob: 590fe31dc4b197cf11d098436076355398e09497 [file] [log] [blame]
Simon Glass1fc54192019-12-08 17:40:17 -07001# SPDX-License-Identifier: GPL-2.0
2#
3# Copyright 2019 Google LLC
4#
5
6config INTEL_APOLLOLAKE
7 bool
8 select FSP_VERSION2
9 select HAVE_FSP
10 select ARCH_MISC_INIT
11 select USE_CAR
Simon Glass736ecc62021-02-23 05:35:42 -050012 select INTEL_SOC
Simon Glass1fc54192019-12-08 17:40:17 -070013 select INTEL_PMC
14 select TPL_X86_TSC_TIMER_NATIVE
15 select SPL_PCH_SUPPORT
16 select TPL_PCH_SUPPORT
Simon Glass97bafc92020-09-22 12:44:51 -060017 select PCIEX_LENGTH_256MB
Simon Glass1fc54192019-12-08 17:40:17 -070018 select PCH_SUPPORT
19 select P2SB
Simon Glassc33aa352020-07-17 08:48:16 -060020 select SMP_AP_WORK
Simon Glassb98b91b2020-09-22 12:45:15 -060021 select INTEL_GMA_SWSMISCI
Simon Glass55109f12020-09-22 12:44:53 -060022 select ACPI_GNVS_EXTERNAL
Simon Glassc238eee2020-12-22 19:30:25 -070023 select TPL_OF_PLATDATA_PARENT
Simon Glass1fc54192019-12-08 17:40:17 -070024 imply ENABLE_MRC_CACHE
25 imply AHCI_PCI
26 imply SCSI
27 imply SCSI_AHCI
28 imply SPI_FLASH
29 imply USB
30 imply USB_EHCI_HCD
31 imply TPL
32 imply SPL
33 imply TPL_X86_16BIT_INIT
34 imply TPL_OF_PLATDATA
35 imply ACPI_PMC
36 imply MMC
37 imply DM_MMC
38 imply MMC_PCI
39 imply MMC_SDHCI
40 imply CMD_MMC
41 imply VIDEO_FSP
42 imply PINCTRL_INTEL
43 imply PINCTRL_INTEL_APL
44 imply HAVE_VBT
45 imply HAVE_X86_FIT
46 imply INTEL_GPIO
47 imply SMP
Wolfgang Wallner1d5bf322020-02-03 14:06:45 +010048 imply HAVE_ITSS
Wolfgang Wallner29998462020-02-04 09:04:56 +010049 imply HAVE_P2SB
Simon Glass659252e2020-02-06 09:54:54 -070050 imply CLK
51 imply CMD_CLK
52 imply CLK_INTEL
Simon Glassfa786042020-02-06 09:55:02 -070053 imply ACPI_GPE
Simon Glassc9cc37d2020-09-22 12:45:03 -060054 imply INTEL_GMA_ACPI
Simon Glass1fc54192019-12-08 17:40:17 -070055
56if INTEL_APOLLOLAKE
57
58config DCACHE_RAM_BASE
59 default 0xfef00000
60
61config DCACHE_RAM_SIZE
62 default 0xc0000
63
64config DCACHE_RAM_MRC_VAR_SIZE
65 default 0xb0000
66
67config CPU_SPECIFIC_OPTIONS
68 def_bool y
69 select SMM_TSEG
70 select X86_RAMTEST
71
72config SMM_TSEG_SIZE
73 hex
74 default 0x800000
75
76config MMCONF_BASE_ADDRESS
77 hex
78 default 0xe0000000
79
80config TPL_SIZE_LIMIT
81 default 0x7800
82
83config CPU_ADDR_BITS
84 default 39
85
86config APL_SPI_FLASH_BOOT
87 bool "Support booting with SPI-flash driver instead memory-mapped SPI"
88 select TPL_SPI_FLASH_SUPPORT
89 select TPL_SPI_SUPPORT
Simon Glassd07f31a2020-10-03 11:31:38 -060090 select TPL_DM_SPI
91 select TPL_DM_SPI_FLASH
Simon Glass1fc54192019-12-08 17:40:17 -070092 help
93 This enables SPI and SPI flash in TPL. Without the this only
94 available boot method is to use memory-mapped SPI. Since this is
95 actually fast and produces a TPL which is 7KB smaller, memory-mapped
96 SPI is the default.
97
98config APL_BOOT_FROM_FAST_SPI_FLASH
99 bool "Boot using SPI flash driver"
100 select APL_SPI_FLASH_BOOT
101 help
102 This option is separate from APL_SPI_FLASH_BOOT since it is useful to
103 be able to compare booting speed with the same build. Enable this to
104 use the SPI-flash driver to load SPL, U-Boot and FSP-M. For technical
105 reasons FSP-S is currently always loaded from memory-mapped SPI. See
106 Apollo Lake's arch_fsp_init_r() for details about that.
107
108config VBT_ADDR
109 default 0xff3f1000
110
111endif