Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * ASPEED FMC/SPI Controller driver |
| 4 | * |
| 5 | * Copyright (c) 2022 ASPEED Corporation. |
| 6 | * Copyright (c) 2022 IBM Corporation. |
| 7 | * |
| 8 | * Author: |
| 9 | * Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
| 10 | * Cedric Le Goater <clg@kaod.org> |
| 11 | */ |
| 12 | |
| 13 | #include <asm/io.h> |
| 14 | #include <clk.h> |
| 15 | #include <common.h> |
| 16 | #include <dm.h> |
| 17 | #include <dm/device_compat.h> |
| 18 | #include <linux/bitops.h> |
| 19 | #include <linux/bug.h> |
| 20 | #include <linux/err.h> |
| 21 | #include <linux/iopoll.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/mtd/spi-nor.h> |
| 24 | #include <linux/sizes.h> |
| 25 | #include <malloc.h> |
| 26 | #include <spi.h> |
| 27 | #include <spi-mem.h> |
| 28 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 29 | #define ASPEED_SPI_MAX_CS 5 |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 30 | |
| 31 | #define CTRL_IO_SINGLE_DATA 0 |
| 32 | #define CTRL_IO_QUAD_DATA BIT(30) |
| 33 | #define CTRL_IO_DUAL_DATA BIT(29) |
| 34 | |
| 35 | #define CTRL_IO_MODE_USER GENMASK(1, 0) |
| 36 | #define CTRL_IO_MODE_CMD_READ BIT(0) |
| 37 | #define CTRL_IO_MODE_CMD_WRITE BIT(1) |
| 38 | #define CTRL_STOP_ACTIVE BIT(2) |
| 39 | |
| 40 | struct aspeed_spi_regs { |
| 41 | u32 conf; /* 0x00 CE Type Setting */ |
| 42 | u32 ctrl; /* 0x04 CE Control */ |
| 43 | u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ |
| 44 | u32 cmd_ctrl; /* 0x0c Command Control */ |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 45 | u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x20 CEx Control */ |
| 46 | u32 _reserved0[3]; /* .. */ |
| 47 | u32 segment_addr[ASPEED_SPI_MAX_CS]; /* 0x30 .. 0x40 Segment Address */ |
| 48 | u32 _reserved1[3]; /* .. */ |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 49 | u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */ |
| 50 | u32 _reserved2[11]; /* .. */ |
| 51 | u32 dma_ctrl; /* 0x80 DMA Control/Status */ |
| 52 | u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ |
| 53 | u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ |
| 54 | u32 dma_len; /* 0x8c DMA Length Register */ |
| 55 | u32 dma_checksum; /* 0x90 Checksum Calculation Result */ |
| 56 | u32 timings[ASPEED_SPI_MAX_CS]; /* 0x94 Read Timing Compensation */ |
| 57 | }; |
| 58 | |
| 59 | struct aspeed_spi_plat { |
| 60 | u8 max_cs; |
| 61 | void __iomem *ahb_base; /* AHB address base for all flash devices. */ |
| 62 | fdt_size_t ahb_sz; /* Overall AHB window size for all flash device. */ |
| 63 | }; |
| 64 | |
| 65 | struct aspeed_spi_flash { |
| 66 | void __iomem *ahb_base; |
| 67 | u32 ahb_decoded_sz; |
| 68 | u32 ce_ctrl_user; |
| 69 | u32 ce_ctrl_read; |
| 70 | }; |
| 71 | |
| 72 | struct aspeed_spi_priv { |
| 73 | u32 num_cs; |
| 74 | struct aspeed_spi_regs *regs; |
| 75 | struct aspeed_spi_info *info; |
| 76 | struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; |
| 77 | }; |
| 78 | |
| 79 | struct aspeed_spi_info { |
| 80 | u32 io_mode_mask; |
| 81 | u32 max_bus_width; |
| 82 | u32 min_decoded_sz; |
| 83 | void (*set_4byte)(struct udevice *bus, u32 cs); |
| 84 | u32 (*segment_start)(struct udevice *bus, u32 reg); |
| 85 | u32 (*segment_end)(struct udevice *bus, u32 reg); |
| 86 | u32 (*segment_reg)(u32 start, u32 end); |
| 87 | }; |
| 88 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 89 | static const struct aspeed_spi_info ast2400_spi_info; |
| 90 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 91 | static u32 aspeed_spi_get_io_mode(u32 bus_width) |
| 92 | { |
| 93 | switch (bus_width) { |
| 94 | case 1: |
| 95 | return CTRL_IO_SINGLE_DATA; |
| 96 | case 2: |
| 97 | return CTRL_IO_DUAL_DATA; |
| 98 | case 4: |
| 99 | return CTRL_IO_QUAD_DATA; |
| 100 | default: |
| 101 | /* keep in default value */ |
| 102 | return CTRL_IO_SINGLE_DATA; |
| 103 | } |
| 104 | } |
| 105 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 106 | static u32 ast2400_spi_segment_start(struct udevice *bus, u32 reg) |
| 107 | { |
| 108 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 109 | u32 start_offset = ((reg >> 16) & 0xff) << 23; |
| 110 | |
| 111 | if (start_offset == 0) |
| 112 | return (u32)plat->ahb_base; |
| 113 | |
| 114 | return (u32)plat->ahb_base + start_offset; |
| 115 | } |
| 116 | |
| 117 | static u32 ast2400_spi_segment_end(struct udevice *bus, u32 reg) |
| 118 | { |
| 119 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 120 | u32 end_offset = ((reg >> 24) & 0xff) << 23; |
| 121 | |
| 122 | /* Meaningless end_offset, set to physical ahb base. */ |
| 123 | if (end_offset == 0) |
| 124 | return (u32)plat->ahb_base; |
| 125 | |
| 126 | return (u32)plat->ahb_base + end_offset; |
| 127 | } |
| 128 | |
| 129 | static u32 ast2400_spi_segment_reg(u32 start, u32 end) |
| 130 | { |
| 131 | if (start == end) |
| 132 | return 0; |
| 133 | |
| 134 | return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24); |
| 135 | } |
| 136 | |
| 137 | static void ast2400_fmc_chip_set_4byte(struct udevice *bus, u32 cs) |
| 138 | { |
| 139 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 140 | u32 reg_val; |
| 141 | |
| 142 | reg_val = readl(&priv->regs->ctrl); |
| 143 | reg_val |= 0x1 << cs; |
| 144 | writel(reg_val, &priv->regs->ctrl); |
| 145 | } |
| 146 | |
| 147 | static void ast2400_spi_chip_set_4byte(struct udevice *bus, u32 cs) |
| 148 | { |
| 149 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 150 | struct aspeed_spi_flash *flash = &priv->flashes[cs]; |
| 151 | |
| 152 | flash->ce_ctrl_read |= BIT(13); |
| 153 | writel(flash->ce_ctrl_read, &priv->regs->ctrl); |
| 154 | } |
| 155 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 156 | static u32 ast2500_spi_segment_start(struct udevice *bus, u32 reg) |
| 157 | { |
| 158 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 159 | u32 start_offset = ((reg >> 16) & 0xff) << 23; |
| 160 | |
| 161 | if (start_offset == 0) |
| 162 | return (u32)plat->ahb_base; |
| 163 | |
| 164 | return (u32)plat->ahb_base + start_offset; |
| 165 | } |
| 166 | |
| 167 | static u32 ast2500_spi_segment_end(struct udevice *bus, u32 reg) |
| 168 | { |
| 169 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 170 | u32 end_offset = ((reg >> 24) & 0xff) << 23; |
| 171 | |
| 172 | /* Meaningless end_offset, set to physical ahb base. */ |
| 173 | if (end_offset == 0) |
| 174 | return (u32)plat->ahb_base; |
| 175 | |
| 176 | return (u32)plat->ahb_base + end_offset; |
| 177 | } |
| 178 | |
| 179 | static u32 ast2500_spi_segment_reg(u32 start, u32 end) |
| 180 | { |
| 181 | if (start == end) |
| 182 | return 0; |
| 183 | |
| 184 | return ((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24); |
| 185 | } |
| 186 | |
| 187 | static void ast2500_spi_chip_set_4byte(struct udevice *bus, u32 cs) |
| 188 | { |
| 189 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 190 | u32 reg_val; |
| 191 | |
| 192 | reg_val = readl(&priv->regs->ctrl); |
| 193 | reg_val |= 0x1 << cs; |
| 194 | writel(reg_val, &priv->regs->ctrl); |
| 195 | } |
| 196 | |
| 197 | static u32 ast2600_spi_segment_start(struct udevice *bus, u32 reg) |
| 198 | { |
| 199 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 200 | u32 start_offset = (reg << 16) & 0x0ff00000; |
| 201 | |
| 202 | if (start_offset == 0) |
| 203 | return (u32)plat->ahb_base; |
| 204 | |
| 205 | return (u32)plat->ahb_base + start_offset; |
| 206 | } |
| 207 | |
| 208 | static u32 ast2600_spi_segment_end(struct udevice *bus, u32 reg) |
| 209 | { |
| 210 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 211 | u32 end_offset = reg & 0x0ff00000; |
| 212 | |
| 213 | /* Meaningless end_offset, set to physical ahb base. */ |
| 214 | if (end_offset == 0) |
| 215 | return (u32)plat->ahb_base; |
| 216 | |
| 217 | return (u32)plat->ahb_base + end_offset + 0x100000; |
| 218 | } |
| 219 | |
| 220 | static u32 ast2600_spi_segment_reg(u32 start, u32 end) |
| 221 | { |
| 222 | if (start == end) |
| 223 | return 0; |
| 224 | |
| 225 | return ((start & 0x0ff00000) >> 16) | ((end - 0x100000) & 0x0ff00000); |
| 226 | } |
| 227 | |
| 228 | static void ast2600_spi_chip_set_4byte(struct udevice *bus, u32 cs) |
| 229 | { |
| 230 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 231 | u32 reg_val; |
| 232 | |
| 233 | reg_val = readl(&priv->regs->ctrl); |
| 234 | reg_val |= 0x11 << cs; |
| 235 | writel(reg_val, &priv->regs->ctrl); |
| 236 | } |
| 237 | |
| 238 | static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, |
| 239 | size_t len) |
| 240 | { |
| 241 | size_t offset = 0; |
| 242 | |
| 243 | if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && |
| 244 | IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { |
| 245 | readsl(ahb_base, buf, len >> 2); |
| 246 | offset = len & ~0x3; |
| 247 | len -= offset; |
| 248 | } |
| 249 | |
| 250 | readsb(ahb_base, (u8 *)buf + offset, len); |
| 251 | |
| 252 | return 0; |
| 253 | } |
| 254 | |
| 255 | static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, |
| 256 | size_t len) |
| 257 | { |
| 258 | size_t offset = 0; |
| 259 | |
| 260 | if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && |
| 261 | IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { |
| 262 | writesl(ahb_base, buf, len >> 2); |
| 263 | offset = len & ~0x3; |
| 264 | len -= offset; |
| 265 | } |
| 266 | |
| 267 | writesb(ahb_base, (u8 *)buf + offset, len); |
| 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | /* |
| 273 | * Currently, only support 1-1-1, 1-1-2 or 1-1-4 |
| 274 | * SPI NOR flash operation format. |
| 275 | */ |
| 276 | static bool aspeed_spi_supports_op(struct spi_slave *slave, |
| 277 | const struct spi_mem_op *op) |
| 278 | { |
| 279 | struct udevice *bus = slave->dev->parent; |
| 280 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 281 | |
| 282 | if (op->cmd.buswidth > 1) |
| 283 | return false; |
| 284 | |
| 285 | if (op->addr.nbytes != 0) { |
| 286 | if (op->addr.buswidth > 1) |
| 287 | return false; |
| 288 | if (op->addr.nbytes < 3 || op->addr.nbytes > 4) |
| 289 | return false; |
| 290 | } |
| 291 | |
| 292 | if (op->dummy.nbytes != 0) { |
| 293 | if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7) |
| 294 | return false; |
| 295 | } |
| 296 | |
| 297 | if (op->data.nbytes != 0 && |
| 298 | op->data.buswidth > priv->info->max_bus_width) |
| 299 | return false; |
| 300 | |
| 301 | if (!spi_mem_default_supports_op(slave, op)) |
| 302 | return false; |
| 303 | |
| 304 | return true; |
| 305 | } |
| 306 | |
| 307 | static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, |
| 308 | const struct spi_mem_op *op) |
| 309 | { |
| 310 | struct udevice *dev = slave->dev; |
| 311 | struct udevice *bus = dev->parent; |
| 312 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 313 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); |
| 314 | u32 cs = slave_plat->cs; |
| 315 | u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; |
| 316 | u32 ce_ctrl_val; |
| 317 | struct aspeed_spi_flash *flash = &priv->flashes[cs]; |
| 318 | u8 dummy_data[16] = {0}; |
| 319 | u8 addr[4] = {0}; |
| 320 | int i; |
| 321 | |
| 322 | dev_dbg(dev, "cmd:%x(%d),addr:%llx(%d),dummy:%d(%d),data_len:0x%x(%d)\n", |
| 323 | op->cmd.opcode, op->cmd.buswidth, op->addr.val, |
| 324 | op->addr.buswidth, op->dummy.nbytes, op->dummy.buswidth, |
| 325 | op->data.nbytes, op->data.buswidth); |
| 326 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 327 | if (priv->info == &ast2400_spi_info) |
| 328 | ce_ctrl_reg = (u32)&priv->regs->ctrl; |
| 329 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 330 | /* |
| 331 | * Set controller to 4-byte address mode |
| 332 | * if flash is in 4-byte address mode. |
| 333 | */ |
| 334 | if (op->cmd.opcode == SPINOR_OP_EN4B) |
| 335 | priv->info->set_4byte(bus, cs); |
| 336 | |
| 337 | /* Start user mode */ |
| 338 | ce_ctrl_val = flash->ce_ctrl_user; |
| 339 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 340 | ce_ctrl_val &= (~CTRL_STOP_ACTIVE); |
| 341 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 342 | |
| 343 | /* Send command */ |
| 344 | aspeed_spi_write_to_ahb(flash->ahb_base, &op->cmd.opcode, 1); |
| 345 | |
| 346 | /* Send address */ |
| 347 | for (i = op->addr.nbytes; i > 0; i--) { |
| 348 | addr[op->addr.nbytes - i] = |
| 349 | ((u32)op->addr.val >> ((i - 1) * 8)) & 0xff; |
| 350 | } |
| 351 | |
| 352 | /* Change io_mode */ |
| 353 | ce_ctrl_val &= ~priv->info->io_mode_mask; |
| 354 | ce_ctrl_val |= aspeed_spi_get_io_mode(op->addr.buswidth); |
| 355 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 356 | aspeed_spi_write_to_ahb(flash->ahb_base, addr, op->addr.nbytes); |
| 357 | |
| 358 | /* Send dummy cycles */ |
| 359 | aspeed_spi_write_to_ahb(flash->ahb_base, dummy_data, op->dummy.nbytes); |
| 360 | |
| 361 | /* Change io_mode */ |
| 362 | ce_ctrl_val &= ~priv->info->io_mode_mask; |
| 363 | ce_ctrl_val |= aspeed_spi_get_io_mode(op->data.buswidth); |
| 364 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 365 | |
| 366 | /* Send data */ |
| 367 | if (op->data.dir == SPI_MEM_DATA_OUT) { |
| 368 | aspeed_spi_write_to_ahb(flash->ahb_base, op->data.buf.out, |
| 369 | op->data.nbytes); |
| 370 | } else { |
| 371 | aspeed_spi_read_from_ahb(flash->ahb_base, op->data.buf.in, |
| 372 | op->data.nbytes); |
| 373 | } |
| 374 | |
| 375 | ce_ctrl_val |= CTRL_STOP_ACTIVE; |
| 376 | writel(ce_ctrl_val, ce_ctrl_reg); |
| 377 | |
| 378 | /* Restore controller setting. */ |
| 379 | writel(flash->ce_ctrl_read, ce_ctrl_reg); |
| 380 | |
| 381 | return 0; |
| 382 | } |
| 383 | |
| 384 | static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) |
| 385 | { |
| 386 | struct udevice *bus = dev->parent; |
| 387 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
| 388 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 389 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 390 | u32 cs = slave_plat->cs; |
| 391 | |
| 392 | if (cs >= plat->max_cs) { |
| 393 | dev_err(dev, "invalid CS %u\n", cs); |
| 394 | return NULL; |
| 395 | } |
| 396 | |
| 397 | return &priv->flashes[cs]; |
| 398 | } |
| 399 | |
| 400 | static void aspeed_spi_decoded_base_calculate(struct udevice *bus) |
| 401 | { |
| 402 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 403 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 404 | u32 cs; |
| 405 | |
| 406 | priv->flashes[0].ahb_base = plat->ahb_base; |
| 407 | |
| 408 | for (cs = 1; cs < plat->max_cs; cs++) { |
| 409 | priv->flashes[cs].ahb_base = |
| 410 | priv->flashes[cs - 1].ahb_base + |
| 411 | priv->flashes[cs - 1].ahb_decoded_sz; |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | static void aspeed_spi_decoded_range_set(struct udevice *bus) |
| 416 | { |
| 417 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 418 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 419 | u32 decoded_reg_val; |
| 420 | u32 start_addr, end_addr; |
| 421 | u32 cs; |
| 422 | |
| 423 | for (cs = 0; cs < plat->max_cs; cs++) { |
| 424 | start_addr = (u32)priv->flashes[cs].ahb_base; |
| 425 | end_addr = (u32)priv->flashes[cs].ahb_base + |
| 426 | priv->flashes[cs].ahb_decoded_sz; |
| 427 | |
| 428 | decoded_reg_val = priv->info->segment_reg(start_addr, end_addr); |
| 429 | |
| 430 | writel(decoded_reg_val, &priv->regs->segment_addr[cs]); |
| 431 | |
| 432 | dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%x, end: 0x%x\n", |
| 433 | cs, decoded_reg_val, start_addr, end_addr); |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | static int aspeed_spi_decoded_range_config(struct udevice *bus) |
| 438 | { |
| 439 | aspeed_spi_decoded_base_calculate(bus); |
| 440 | aspeed_spi_decoded_range_set(bus); |
| 441 | |
| 442 | return 0; |
| 443 | } |
| 444 | |
| 445 | /* |
| 446 | * Initialize SPI controller for each chip select. |
| 447 | * Here, only the minimum decode range is configured |
| 448 | * in order to get device (SPI NOR flash) information |
| 449 | * at the early stage. |
| 450 | */ |
| 451 | static int aspeed_spi_ctrl_init(struct udevice *bus) |
| 452 | { |
| 453 | int ret; |
| 454 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 455 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 456 | u32 cs; |
| 457 | u32 reg_val; |
| 458 | u32 decoded_sz; |
| 459 | |
| 460 | /* Enable write capability for all CS. */ |
| 461 | reg_val = readl(&priv->regs->conf); |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 462 | if (priv->info == &ast2400_spi_info) { |
| 463 | writel(reg_val | BIT(0), &priv->regs->conf); |
| 464 | } else { |
| 465 | writel(reg_val | (GENMASK(plat->max_cs - 1, 0) << 16), |
| 466 | &priv->regs->conf); |
| 467 | } |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 468 | |
| 469 | memset(priv->flashes, 0x0, |
| 470 | sizeof(struct aspeed_spi_flash) * ASPEED_SPI_MAX_CS); |
| 471 | |
| 472 | /* Initial user mode. */ |
| 473 | for (cs = 0; cs < priv->num_cs; cs++) { |
| 474 | priv->flashes[cs].ce_ctrl_user = |
| 475 | (CTRL_STOP_ACTIVE | CTRL_IO_MODE_USER); |
| 476 | } |
| 477 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 478 | /* |
| 479 | * SPI1 on AST2400 only supports CS0. |
| 480 | * It is unnecessary to configure segment address register. |
| 481 | */ |
| 482 | if (priv->info == &ast2400_spi_info) { |
| 483 | priv->flashes[cs].ahb_base = plat->ahb_base; |
| 484 | priv->flashes[cs].ahb_decoded_sz = 0x10000000; |
| 485 | return 0; |
| 486 | } |
| 487 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 488 | /* Assign basic AHB decoded size for each CS. */ |
| 489 | for (cs = 0; cs < plat->max_cs; cs++) { |
| 490 | reg_val = readl(&priv->regs->segment_addr[cs]); |
| 491 | decoded_sz = priv->info->segment_end(bus, reg_val) - |
| 492 | priv->info->segment_start(bus, reg_val); |
| 493 | |
| 494 | if (decoded_sz < priv->info->min_decoded_sz) |
| 495 | decoded_sz = priv->info->min_decoded_sz; |
| 496 | |
| 497 | priv->flashes[cs].ahb_decoded_sz = decoded_sz; |
| 498 | } |
| 499 | |
| 500 | ret = aspeed_spi_decoded_range_config(bus); |
| 501 | |
| 502 | return ret; |
| 503 | } |
| 504 | |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 505 | static const struct aspeed_spi_info ast2400_fmc_info = { |
| 506 | .io_mode_mask = 0x70000000, |
| 507 | .max_bus_width = 2, |
| 508 | .min_decoded_sz = 0x800000, |
| 509 | .set_4byte = ast2400_fmc_chip_set_4byte, |
| 510 | .segment_start = ast2400_spi_segment_start, |
| 511 | .segment_end = ast2400_spi_segment_end, |
| 512 | .segment_reg = ast2400_spi_segment_reg, |
| 513 | }; |
| 514 | |
| 515 | static const struct aspeed_spi_info ast2400_spi_info = { |
| 516 | .io_mode_mask = 0x70000000, |
| 517 | .max_bus_width = 2, |
| 518 | .min_decoded_sz = 0x800000, |
| 519 | .set_4byte = ast2400_spi_chip_set_4byte, |
| 520 | .segment_start = ast2400_spi_segment_start, |
| 521 | .segment_end = ast2400_spi_segment_end, |
| 522 | .segment_reg = ast2400_spi_segment_reg, |
| 523 | }; |
| 524 | |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 525 | static const struct aspeed_spi_info ast2500_fmc_info = { |
| 526 | .io_mode_mask = 0x70000000, |
| 527 | .max_bus_width = 2, |
| 528 | .min_decoded_sz = 0x800000, |
| 529 | .set_4byte = ast2500_spi_chip_set_4byte, |
| 530 | .segment_start = ast2500_spi_segment_start, |
| 531 | .segment_end = ast2500_spi_segment_end, |
| 532 | .segment_reg = ast2500_spi_segment_reg, |
| 533 | }; |
| 534 | |
| 535 | /* |
| 536 | * There are some different between FMC and SPI controllers. |
| 537 | * For example, DMA operation, but this isn't implemented currently. |
| 538 | */ |
| 539 | static const struct aspeed_spi_info ast2500_spi_info = { |
| 540 | .io_mode_mask = 0x70000000, |
| 541 | .max_bus_width = 2, |
| 542 | .min_decoded_sz = 0x800000, |
| 543 | .set_4byte = ast2500_spi_chip_set_4byte, |
| 544 | .segment_start = ast2500_spi_segment_start, |
| 545 | .segment_end = ast2500_spi_segment_end, |
| 546 | .segment_reg = ast2500_spi_segment_reg, |
| 547 | }; |
| 548 | |
| 549 | static const struct aspeed_spi_info ast2600_fmc_info = { |
| 550 | .io_mode_mask = 0xf0000000, |
| 551 | .max_bus_width = 4, |
| 552 | .min_decoded_sz = 0x200000, |
| 553 | .set_4byte = ast2600_spi_chip_set_4byte, |
| 554 | .segment_start = ast2600_spi_segment_start, |
| 555 | .segment_end = ast2600_spi_segment_end, |
| 556 | .segment_reg = ast2600_spi_segment_reg, |
| 557 | }; |
| 558 | |
| 559 | static const struct aspeed_spi_info ast2600_spi_info = { |
| 560 | .io_mode_mask = 0xf0000000, |
| 561 | .max_bus_width = 4, |
| 562 | .min_decoded_sz = 0x200000, |
| 563 | .set_4byte = ast2600_spi_chip_set_4byte, |
| 564 | .segment_start = ast2600_spi_segment_start, |
| 565 | .segment_end = ast2600_spi_segment_end, |
| 566 | .segment_reg = ast2600_spi_segment_reg, |
| 567 | }; |
| 568 | |
| 569 | static int aspeed_spi_claim_bus(struct udevice *dev) |
| 570 | { |
| 571 | struct udevice *bus = dev->parent; |
| 572 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
| 573 | |
| 574 | dev_dbg(bus, "%s: claim bus CS%u\n", bus->name, slave_plat->cs); |
| 575 | |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | static int aspeed_spi_release_bus(struct udevice *dev) |
| 580 | { |
| 581 | struct udevice *bus = dev->parent; |
| 582 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
| 583 | |
| 584 | dev_dbg(bus, "%s: release bus CS%u\n", bus->name, slave_plat->cs); |
| 585 | |
| 586 | if (!aspeed_spi_get_flash(dev)) |
| 587 | return -ENODEV; |
| 588 | |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | static int aspeed_spi_set_mode(struct udevice *bus, uint mode) |
| 593 | { |
| 594 | dev_dbg(bus, "%s: setting mode to %x\n", bus->name, mode); |
| 595 | |
| 596 | return 0; |
| 597 | } |
| 598 | |
| 599 | static int aspeed_spi_set_speed(struct udevice *bus, uint hz) |
| 600 | { |
| 601 | dev_dbg(bus, "%s: setting speed to %u\n", bus->name, hz); |
| 602 | /* |
| 603 | * ASPEED SPI controller supports multiple CS with different |
| 604 | * clock frequency. We cannot distinguish which CS here. |
| 605 | * Thus, the related implementation is postponed to claim_bus. |
| 606 | */ |
| 607 | |
| 608 | return 0; |
| 609 | } |
| 610 | |
| 611 | static int apseed_spi_of_to_plat(struct udevice *bus) |
| 612 | { |
| 613 | struct aspeed_spi_plat *plat = dev_get_plat(bus); |
| 614 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 615 | |
| 616 | priv->regs = (void __iomem *)devfdt_get_addr_index(bus, 0); |
| 617 | if ((u32)priv->regs == FDT_ADDR_T_NONE) { |
| 618 | dev_err(bus, "wrong ctrl base\n"); |
| 619 | return -ENODEV; |
| 620 | } |
| 621 | |
| 622 | plat->ahb_base = |
| 623 | (void __iomem *)devfdt_get_addr_size_index(bus, 1, &plat->ahb_sz); |
| 624 | if ((u32)plat->ahb_base == FDT_ADDR_T_NONE) { |
| 625 | dev_err(bus, "wrong AHB base\n"); |
| 626 | return -ENODEV; |
| 627 | } |
| 628 | |
| 629 | plat->max_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); |
| 630 | if (plat->max_cs > ASPEED_SPI_MAX_CS) |
| 631 | return -EINVAL; |
| 632 | |
| 633 | dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%lx\n", |
| 634 | (u32)priv->regs, plat->ahb_base, plat->ahb_sz); |
| 635 | dev_dbg(bus, "max_cs = %d\n", plat->max_cs); |
| 636 | |
| 637 | return 0; |
| 638 | } |
| 639 | |
| 640 | static int aspeed_spi_probe(struct udevice *bus) |
| 641 | { |
| 642 | int ret; |
| 643 | struct aspeed_spi_priv *priv = dev_get_priv(bus); |
| 644 | struct udevice *dev; |
| 645 | |
| 646 | priv->info = (struct aspeed_spi_info *)dev_get_driver_data(bus); |
| 647 | |
| 648 | priv->num_cs = 0; |
| 649 | for (device_find_first_child(bus, &dev); dev; |
| 650 | device_find_next_child(&dev)) { |
| 651 | priv->num_cs++; |
| 652 | } |
| 653 | |
| 654 | if (priv->num_cs > ASPEED_SPI_MAX_CS) |
| 655 | return -EINVAL; |
| 656 | |
| 657 | ret = aspeed_spi_ctrl_init(bus); |
| 658 | |
| 659 | return ret; |
| 660 | } |
| 661 | |
| 662 | static const struct spi_controller_mem_ops aspeed_spi_mem_ops = { |
| 663 | .supports_op = aspeed_spi_supports_op, |
| 664 | .exec_op = aspeed_spi_exec_op_user_mode, |
| 665 | }; |
| 666 | |
| 667 | static const struct dm_spi_ops aspeed_spi_ops = { |
| 668 | .claim_bus = aspeed_spi_claim_bus, |
| 669 | .release_bus = aspeed_spi_release_bus, |
| 670 | .set_speed = aspeed_spi_set_speed, |
| 671 | .set_mode = aspeed_spi_set_mode, |
| 672 | .mem_ops = &aspeed_spi_mem_ops, |
| 673 | }; |
| 674 | |
| 675 | static const struct udevice_id aspeed_spi_ids[] = { |
Chin-Ting Kuo | 5150e90 | 2022-08-19 17:01:06 +0800 | [diff] [blame] | 676 | { .compatible = "aspeed,ast2400-fmc", .data = (ulong)&ast2400_fmc_info, }, |
| 677 | { .compatible = "aspeed,ast2400-spi", .data = (ulong)&ast2400_spi_info, }, |
Chin-Ting Kuo | 4daa6bb | 2022-08-19 17:01:04 +0800 | [diff] [blame] | 678 | { .compatible = "aspeed,ast2500-fmc", .data = (ulong)&ast2500_fmc_info, }, |
| 679 | { .compatible = "aspeed,ast2500-spi", .data = (ulong)&ast2500_spi_info, }, |
| 680 | { .compatible = "aspeed,ast2600-fmc", .data = (ulong)&ast2600_fmc_info, }, |
| 681 | { .compatible = "aspeed,ast2600-spi", .data = (ulong)&ast2600_spi_info, }, |
| 682 | { } |
| 683 | }; |
| 684 | |
| 685 | U_BOOT_DRIVER(aspeed_spi) = { |
| 686 | .name = "aspeed_spi_smc", |
| 687 | .id = UCLASS_SPI, |
| 688 | .of_match = aspeed_spi_ids, |
| 689 | .ops = &aspeed_spi_ops, |
| 690 | .of_to_plat = apseed_spi_of_to_plat, |
| 691 | .plat_auto = sizeof(struct aspeed_spi_plat), |
| 692 | .priv_auto = sizeof(struct aspeed_spi_priv), |
| 693 | .probe = aspeed_spi_probe, |
| 694 | }; |