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wdenk945af8d2003-07-16 21:53:01 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenk945af8d2003-07-16 21:53:01 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
wdenkcbd8a352004-02-24 02:00:03 +000032#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
Detlev Zundelfd428c02010-03-12 10:01:12 +010033#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
wdenk945af8d2003-07-16 21:53:01 +000034#define CONFIG_ICECUBE 1 /* ... on IceCube board */
35
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036/*
37 * Valid values for CONFIG_SYS_TEXT_BASE are:
38 * 0xFFF00000 boot high (standard configuration)
39 * 0xFF000000 boot low for 16 MiB boards
40 * 0xFF800000 boot low for 8 MiB boards
41 * 0x00100000 boot from RAM (for testing only)
42 */
43#ifndef CONFIG_SYS_TEXT_BASE
44#define CONFIG_SYS_TEXT_BASE 0xFFF00000
45#endif
46
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenk945af8d2003-07-16 21:53:01 +000048
Becky Bruce31d82672008-05-08 19:02:12 -050049#define CONFIG_HIGH_BATS 1 /* High BATs supported */
50
wdenk945af8d2003-07-16 21:53:01 +000051/*
52 * Serial console configuration
53 */
54#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
55#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk945af8d2003-07-16 21:53:01 +000057
wdenk96e48cf2003-08-05 18:22:44 +000058
wdenk96e48cf2003-08-05 18:22:44 +000059/*
60 * PCI Mapping:
61 * 0x40000000 - 0x4fffffff - PCI Memory
62 * 0x50000000 - 0x50ffffff - PCI IO Space
63 */
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020064#define CONFIG_PCI
65
66#if defined(CONFIG_PCI)
wdenk96e48cf2003-08-05 18:22:44 +000067#define CONFIG_PCI_PNP 1
68#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050069#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenk96e48cf2003-08-05 18:22:44 +000070
71#define CONFIG_PCI_MEM_BUS 0x40000000
72#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
73#define CONFIG_PCI_MEM_SIZE 0x10000000
74
75#define CONFIG_PCI_IO_BUS 0x50000000
76#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
77#define CONFIG_PCI_IO_SIZE 0x01000000
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020078#endif
wdenk96e48cf2003-08-05 18:22:44 +000079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_XLB_PIPELINING 1
wdenke1599e82004-10-10 23:27:33 +000081
Marian Balakowicz63ff0042005-10-28 22:30:33 +020082#define CONFIG_MII 1
wdenk96e48cf2003-08-05 18:22:44 +000083#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkf54ebdf2003-09-17 15:10:32 +000085#define CONFIG_NS8382X 1
wdenk96e48cf2003-08-05 18:22:44 +000086
wdenk132ba5f2004-02-27 08:20:54 +000087/* Partitions */
88#define CONFIG_MAC_PARTITION
89#define CONFIG_DOS_PARTITION
wdenk64f70be2004-09-28 20:34:50 +000090#define CONFIG_ISO_PARTITION
wdenk132ba5f2004-02-27 08:20:54 +000091
wdenk80885a92004-02-26 23:46:20 +000092/* USB */
Markus Klotzbuecherae3b7702006-11-27 11:46:46 +010093#define CONFIG_USB_OHCI_NEW
wdenk80885a92004-02-26 23:46:20 +000094#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_OHCI_BE_CONTROLLER
96#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
97#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
98#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
99#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
100#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Markus Klotzbuecherae3b7702006-11-27 11:46:46 +0100101
wdenk414eec32005-04-02 22:37:54 +0000102#define CONFIG_TIMESTAMP /* Print image info with timestamp */
103
wdenk945af8d2003-07-16 21:53:01 +0000104
Jon Loeliger348f2582007-07-08 13:46:18 -0500105/*
Jon Loeliger11799432007-07-10 09:02:57 -0500106 * BOOTP options
107 */
108#define CONFIG_BOOTP_BOOTFILESIZE
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_GATEWAY
111#define CONFIG_BOOTP_HOSTNAME
112
113
114/*
Jon Loeliger348f2582007-07-08 13:46:18 -0500115 * Command line configuration.
116 */
117#include <config_cmd_default.h>
118
119#define CONFIG_CMD_EEPROM
120#define CONFIG_CMD_FAT
121#define CONFIG_CMD_I2C
122#define CONFIG_CMD_IDE
123#define CONFIG_CMD_NFS
124#define CONFIG_CMD_SNTP
Jon Loeliger11799432007-07-10 09:02:57 -0500125#define CONFIG_CMD_USB
126
127#if defined(CONFIG_PCI)
128#define CONFIG_CMD_PCI
129#endif
Jon Loeliger348f2582007-07-08 13:46:18 -0500130
wdenk945af8d2003-07-16 21:53:01 +0000131
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200132#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133# define CONFIG_SYS_LOWBOOT 1
134# define CONFIG_SYS_LOWBOOT16 1
wdenk5cf9da42003-11-07 13:42:26 +0000135#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200136#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100137#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100139#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140# define CONFIG_SYS_LOWBOOT 1
141# define CONFIG_SYS_LOWBOOT08 1
wdenk5cf9da42003-11-07 13:42:26 +0000142#endif
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100143#endif
wdenk5cf9da42003-11-07 13:42:26 +0000144
wdenk945af8d2003-07-16 21:53:01 +0000145/*
146 * Autobooting
147 */
148#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk5cf9da42003-11-07 13:42:26 +0000149
150#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100151 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk5cf9da42003-11-07 13:42:26 +0000152 "echo"
153
154#undef CONFIG_BOOTARGS
155
156#define CONFIG_EXTRA_ENV_SETTINGS \
157 "netdev=eth0\0" \
158 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100159 "nfsroot=${serverip}:${rootpath}\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000160 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100161 "addip=setenv bootargs ${bootargs} " \
162 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
163 ":${hostname}:${netdev}:off panic=1\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000164 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100165 "bootm ${kernel_addr}\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000166 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100167 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
168 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000169 "rootpath=/opt/eldk/ppc_82xx\0" \
170 "bootfile=/tftpboot/MPC5200/uImage\0" \
171 ""
172
173#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk945af8d2003-07-16 21:53:01 +0000174
wdenkacf98e72003-09-16 11:39:10 +0000175/*
176 * IPB Bus clocking configuration.
177 */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100178#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100180#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkacf98e72003-09-16 11:39:10 +0000182#endif
Stefan Roesee59581c2006-11-28 17:55:49 +0100183
184/* pass open firmware flat tree */
Grant Likelycf2817a2007-09-06 09:46:23 -0600185#define CONFIG_OF_LIBFDT 1
Stefan Roesee59581c2006-11-28 17:55:49 +0100186#define CONFIG_OF_BOARD_SETUP 1
187
Stefan Roesee59581c2006-11-28 17:55:49 +0100188#define OF_CPU "PowerPC,5200@0"
189#define OF_SOC "soc5200@f0000000"
Domen Puncer39f23cd2007-04-20 11:13:16 +0200190#define OF_TBCLK (bd->bi_busfreq / 4)
Stefan Roesee59581c2006-11-28 17:55:49 +0100191#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
192
wdenk945af8d2003-07-16 21:53:01 +0000193/*
194 * I2C configuration
195 */
wdenk531716e2003-09-13 19:01:12 +0000196#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
dzuab209d52003-09-30 14:08:43 +0000198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
200#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk531716e2003-09-13 19:01:12 +0000201
202/*
203 * EEPROM configuration
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
206#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
207#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
208#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenk945af8d2003-07-16 21:53:01 +0000209
210/*
211 * Flash configuration
212 */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100213#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_FLASH_BASE 0xFE000000
215#define CONFIG_SYS_FLASH_SIZE 0x01000000
216#if !defined(CONFIG_SYS_LOWBOOT)
217#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
218#else /* CONFIG_SYS_LOWBOOT */
219#if defined(CONFIG_SYS_LOWBOOT08)
220# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100221#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#if defined(CONFIG_SYS_LOWBOOT16)
223#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100224#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#endif /* CONFIG_SYS_LOWBOOT */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100226#else /* !CONFIG_LITE5200B (IceCube)*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_FLASH_BASE 0xFF000000
228#define CONFIG_SYS_FLASH_SIZE 0x01000000
229#if !defined(CONFIG_SYS_LOWBOOT)
230#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
231#else /* CONFIG_SYS_LOWBOOT */
232#if defined(CONFIG_SYS_LOWBOOT08)
233#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
wdenk7152b1d2003-09-05 23:19:14 +0000234#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#if defined(CONFIG_SYS_LOWBOOT16)
236#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
wdenk5cf9da42003-11-07 13:42:26 +0000237#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#endif /* CONFIG_SYS_LOWBOOT */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100239#endif /* CONFIG_LITE5200B */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
wdenk7152b1d2003-09-05 23:19:14 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk945af8d2003-07-16 21:53:01 +0000243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
245#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk945af8d2003-07-16 21:53:01 +0000246
wdenk96e48cf2003-08-05 18:22:44 +0000247#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
wdenk945af8d2003-07-16 21:53:01 +0000248
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100249#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200250#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_FLASH_CFI
252#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100253#endif
254
wdenk945af8d2003-07-16 21:53:01 +0000255
256/*
257 * Environment settings
258 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200259#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200260#define CONFIG_ENV_SIZE 0x10000
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100261#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200262#define CONFIG_ENV_SECT_SIZE 0x20000
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100263#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200264#define CONFIG_ENV_SECT_SIZE 0x10000
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100265#endif
wdenk96e48cf2003-08-05 18:22:44 +0000266#define CONFIG_ENV_OVERWRITE 1
wdenk945af8d2003-07-16 21:53:01 +0000267
268/*
269 * Memory map
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_MBAR 0xF0000000
272#define CONFIG_SYS_SDRAM_BASE 0x00000000
273#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenk945af8d2003-07-16 21:53:01 +0000274
275/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200277#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
wdenk945af8d2003-07-16 21:53:01 +0000278
279
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200280#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk945af8d2003-07-16 21:53:01 +0000282
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200283#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
285# define CONFIG_SYS_RAMBOOT 1
wdenk945af8d2003-07-16 21:53:01 +0000286#endif
287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
Wolfgang Denkd2e22732010-07-01 09:44:39 +0200289#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk945af8d2003-07-16 21:53:01 +0000291
292/*
293 * Ethernet configuration
294 */
wdenkcbd8a352004-02-24 02:00:03 +0000295#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800296#define CONFIG_MPC5xxx_FEC_MII100
wdenk04a85b32004-04-15 18:22:41 +0000297/*
Ben Warren86321fc2009-02-05 23:58:25 -0800298 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
wdenk7e780362004-04-08 22:31:29 +0000299 */
Ben Warren86321fc2009-02-05 23:58:25 -0800300/* #define CONFIG_MPC5xxx_FEC_MII10 */
wdenkd4ca31c2004-01-02 14:00:00 +0000301#define CONFIG_PHY_ADDR 0x00
wdenk945af8d2003-07-16 21:53:01 +0000302
303/*
304 * GPIO configuration
305 */
wdenkb2001f22003-12-20 22:45:10 +0000306#ifdef CONFIG_MPC5200_DDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
wdenkb2001f22003-12-20 22:45:10 +0000308#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
wdenkb2001f22003-12-20 22:45:10 +0000310#endif
wdenk945af8d2003-07-16 21:53:01 +0000311
312/*
313 * Miscellaneous configurable options
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_LONGHELP /* undef to save memory */
316#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500317#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk945af8d2003-07-16 21:53:01 +0000319#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk945af8d2003-07-16 21:53:01 +0000321#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
323#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
324#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk945af8d2003-07-16 21:53:01 +0000325
Wolfgang Denkd2e22732010-07-01 09:44:39 +0200326#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
327#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
328#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
331#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk945af8d2003-07-16 21:53:01 +0000332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk945af8d2003-07-16 21:53:01 +0000334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk945af8d2003-07-16 21:53:01 +0000336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500338#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger348f2582007-07-08 13:46:18 -0500340#endif
341
wdenk945af8d2003-07-16 21:53:01 +0000342/*
343 * Various low-level settings
344 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
346#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenk945af8d2003-07-16 21:53:01 +0000347
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100348#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
350#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
351#define CONFIG_SYS_CS1_CFG 0x00047800
352#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
353#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
354#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
355#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
356#define CONFIG_SYS_BOOTCS_CFG 0x00047800
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100357#else /* IceCube aka Lite5200 */
wdenkb2001f22003-12-20 22:45:10 +0000358#ifdef CONFIG_MPC5200_DDR
359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
361#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
362#define CONFIG_SYS_BOOTCS_CFG 0x00047801
363#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
364#define CONFIG_SYS_CS1_SIZE 0x00800000
365#define CONFIG_SYS_CS1_CFG 0x00047800
wdenkb2001f22003-12-20 22:45:10 +0000366
367#else /* !CONFIG_MPC5200_DDR */
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
370#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
371#define CONFIG_SYS_BOOTCS_CFG 0x00047801
372#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
373#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenk945af8d2003-07-16 21:53:01 +0000374
wdenkb2001f22003-12-20 22:45:10 +0000375#endif /* CONFIG_MPC5200_DDR */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100376#endif /*CONFIG_LITE5200B */
wdenkb2001f22003-12-20 22:45:10 +0000377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_CS_BURST 0x00000000
379#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenk945af8d2003-07-16 21:53:01 +0000380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_RESET_ADDRESS 0xff000000
wdenk945af8d2003-07-16 21:53:01 +0000382
wdenk132ba5f2004-02-27 08:20:54 +0000383/*-----------------------------------------------------------------------
wdenkc3f9d492004-03-14 00:59:59 +0000384 * USB stuff
385 *-----------------------------------------------------------------------
386 */
wdenk4d13cba2004-03-14 14:09:05 +0000387#define CONFIG_USB_CLOCK 0x0001BBBB
388#define CONFIG_USB_CONFIG 0x00001000
wdenkc3f9d492004-03-14 00:59:59 +0000389
390/*-----------------------------------------------------------------------
wdenk132ba5f2004-02-27 08:20:54 +0000391 * IDE/ATA stuff Supports IDE harddisk
392 *-----------------------------------------------------------------------
393 */
394
395#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
396
397#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
398#undef CONFIG_IDE_LED /* LED for ide not supported */
399
400#define CONFIG_IDE_RESET /* reset for ide supported */
401#define CONFIG_IDE_PREINIT
402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
404#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
wdenk132ba5f2004-02-27 08:20:54 +0000405
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk132ba5f2004-02-27 08:20:54 +0000407
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
wdenk132ba5f2004-02-27 08:20:54 +0000409
410/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
wdenk132ba5f2004-02-27 08:20:54 +0000412
413/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
wdenk132ba5f2004-02-27 08:20:54 +0000415
416/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
wdenk132ba5f2004-02-27 08:20:54 +0000418
419/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_ATA_STRIDE 4
wdenk132ba5f2004-02-27 08:20:54 +0000421
wdenk64f70be2004-09-28 20:34:50 +0000422#define CONFIG_ATAPI 1
423
wdenk945af8d2003-07-16 21:53:01 +0000424#endif /* __CONFIG_H */