Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) 2019 |
| 4 | * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> |
| 5 | */ |
| 6 | |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 7 | #include "armv7-m.dtsi" |
| 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 9 | #include <dt-bindings/clock/imxrt1050-clock.h> |
| 10 | #include <dt-bindings/gpio/gpio.h> |
| 11 | #include <dt-bindings/memory/imxrt-sdram.h> |
| 12 | |
| 13 | / { |
Giulio Benetti | 22aa286 | 2020-04-08 17:11:05 +0200 | [diff] [blame] | 14 | #address-cells = <1>; |
| 15 | #size-cells = <1>; |
| 16 | |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 17 | aliases { |
Giulio Benetti | bb8af5f | 2020-04-08 17:10:21 +0200 | [diff] [blame] | 18 | display0 = &lcdif; |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 19 | gpio0 = &gpio1; |
| 20 | gpio1 = &gpio2; |
| 21 | gpio2 = &gpio3; |
| 22 | gpio3 = &gpio4; |
| 23 | gpio4 = &gpio5; |
| 24 | mmc0 = &usdhc1; |
| 25 | serial0 = &lpuart1; |
| 26 | }; |
| 27 | |
| 28 | clocks { |
Giulio Benetti | 6cd7a9b | 2021-05-13 12:18:39 +0200 | [diff] [blame] | 29 | osc: osc { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 30 | compatible = "fsl,imx-osc", "fixed-clock"; |
| 31 | #clock-cells = <0>; |
| 32 | clock-frequency = <24000000>; |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | soc { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 37 | semc: semc@402f0000 { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 38 | compatible = "fsl,imxrt-semc"; |
| 39 | reg = <0x402f0000 0x4000>; |
| 40 | clocks = <&clks IMXRT1050_CLK_SEMC>; |
| 41 | pinctrl-0 = <&pinctrl_semc>; |
| 42 | pinctrl-names = "default"; |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | |
| 46 | lpuart1: serial@40184000 { |
| 47 | compatible = "fsl,imxrt-lpuart"; |
| 48 | reg = <0x40184000 0x4000>; |
| 49 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 50 | clocks = <&clks IMXRT1050_CLK_LPUART1>; |
| 51 | clock-names = "per"; |
| 52 | status = "disabled"; |
| 53 | }; |
| 54 | |
| 55 | iomuxc: iomuxc@401f8000 { |
| 56 | compatible = "fsl,imxrt-iomuxc"; |
| 57 | reg = <0x401f8000 0x4000>; |
| 58 | fsl,mux_mask = <0x7>; |
| 59 | }; |
| 60 | |
| 61 | clks: ccm@400fc000 { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 62 | compatible = "fsl,imxrt1050-ccm"; |
| 63 | reg = <0x400fc000 0x4000>; |
| 64 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, |
| 65 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 66 | #clock-cells = <1>; |
| 67 | }; |
| 68 | |
| 69 | usdhc1: usdhc@402c0000 { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 70 | compatible = "fsl,imxrt-usdhc"; |
| 71 | reg = <0x402c0000 0x10000>; |
| 72 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 73 | clocks = <&clks IMXRT1050_CLK_USDHC1>; |
| 74 | clock-names = "per"; |
| 75 | bus-width = <4>; |
| 76 | fsl,tuning-start-tap = <20>; |
| 77 | fsl,tuning-step= <2>; |
| 78 | status = "disabled"; |
| 79 | }; |
| 80 | |
| 81 | gpio1: gpio@401b8000 { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 82 | compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; |
| 83 | reg = <0x401b8000 0x4000>; |
| 84 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, |
| 85 | <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 86 | gpio-controller; |
| 87 | #gpio-cells = <2>; |
| 88 | interrupt-controller; |
| 89 | #interrupt-cells = <2>; |
| 90 | }; |
| 91 | |
| 92 | gpio2: gpio@401bc000 { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 93 | compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; |
| 94 | reg = <0x401bc000 0x4000>; |
| 95 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, |
| 96 | <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 97 | gpio-controller; |
| 98 | #gpio-cells = <2>; |
| 99 | interrupt-controller; |
| 100 | #interrupt-cells = <2>; |
| 101 | }; |
| 102 | |
| 103 | gpio3: gpio@401c0000 { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 104 | compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; |
| 105 | reg = <0x401c0000 0x4000>; |
| 106 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, |
| 107 | <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 108 | gpio-controller; |
| 109 | #gpio-cells = <2>; |
| 110 | interrupt-controller; |
| 111 | #interrupt-cells = <2>; |
| 112 | }; |
| 113 | |
| 114 | gpio4: gpio@401c4000 { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 115 | compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; |
| 116 | reg = <0x401c4000 0x4000>; |
| 117 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, |
| 118 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| 119 | gpio-controller; |
| 120 | #gpio-cells = <2>; |
| 121 | interrupt-controller; |
| 122 | #interrupt-cells = <2>; |
| 123 | }; |
| 124 | |
| 125 | gpio5: gpio@400c0000 { |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 126 | compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; |
| 127 | reg = <0x400c0000 0x4000>; |
| 128 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| 129 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| 130 | gpio-controller; |
| 131 | #gpio-cells = <2>; |
| 132 | interrupt-controller; |
| 133 | #interrupt-cells = <2>; |
| 134 | }; |
Giulio Benetti | bb8af5f | 2020-04-08 17:10:21 +0200 | [diff] [blame] | 135 | |
| 136 | lcdif: lcdif@402b8000 { |
Giulio Benetti | 8fde50f | 2020-04-28 18:20:11 +0200 | [diff] [blame] | 137 | compatible = "fsl,imxrt-lcdif"; |
| 138 | reg = <0x402b8000 0x4000>; |
| 139 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
Giulio Benetti | a9a5c33 | 2021-05-13 12:19:35 +0200 | [diff] [blame] | 140 | clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>, |
| 141 | <&clks IMXRT1050_CLK_LCDIF_APB>; |
| 142 | clock-names = "pix", "axi"; |
Giulio Benetti | f2d91e6 | 2021-05-13 12:19:34 +0200 | [diff] [blame] | 143 | assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; |
| 144 | assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; |
Giulio Benetti | 8fde50f | 2020-04-28 18:20:11 +0200 | [diff] [blame] | 145 | status = "disabled"; |
Giulio Benetti | bb8af5f | 2020-04-08 17:10:21 +0200 | [diff] [blame] | 146 | }; |
Giulio Benetti | 5790db9 | 2021-05-13 12:18:40 +0200 | [diff] [blame] | 147 | |
| 148 | gpt1: gpt1@401ec000 { |
| 149 | compatible = "fsl,imxrt-gpt"; |
| 150 | reg = <0x401ec000 0x4000>; |
| 151 | interrupts = <100>; |
| 152 | clocks = <&osc>; |
| 153 | status = "disabled"; |
| 154 | }; |
Giulio Benetti | e12b737 | 2020-01-10 15:47:04 +0100 | [diff] [blame] | 155 | }; |
| 156 | }; |