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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0xFF000000
40
wdenk0f8c9762002-08-19 11:57:05 +000041#if defined (CONFIG_IVMS8_16M)
42# define CONFIG_IDENT_STRING " IVMS8"
43#elif defined (CONFIG_IVMS8_32M)
44# define CONFIG_IDENT_STRING " IVMS8_128"
45#elif defined (CONFIG_IVMS8_64M)
46# define CONFIG_IDENT_STRING " IVMS8_256"
47#endif
48
49#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
50#undef CONFIG_8xx_CONS_SMC2
51#undef CONFIG_8xx_CONS_NONE
52#define CONFIG_BAUDRATE 115200
53
Peter Tyser004eca02009-09-16 22:03:08 -050054#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
55
wdenk0f8c9762002-08-19 11:57:05 +000056#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
57#define CONFIG_8xx_GCLK_FREQ 50331648
58
59#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
60
61#if 0
62#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
63#else
64#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
65#endif
66#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
67
68#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
69 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
70 "nfsaddrs=10.0.0.99:10.0.0.2"
71
72#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk0f8c9762002-08-19 11:57:05 +000074
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76
77#define CONFIG_STATUS_LED 1 /* Status LED enabled */
78
Jon Loeliger348f2582007-07-08 13:46:18 -050079/*
80 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#define CONFIG_CMD_IDE
85
86
wdenk0f8c9762002-08-19 11:57:05 +000087#define CONFIG_MAC_PARTITION
88#define CONFIG_DOS_PARTITION
89
Jon Loeliger7be044e2007-07-09 21:24:19 -050090/*
91 * BOOTP options
92 */
93#define CONFIG_BOOTP_SUBNETMASK
94#define CONFIG_BOOTP_HOSTNAME
95#define CONFIG_BOOTP_BOOTPATH
96#define CONFIG_BOOTP_BOOTFILESIZE
97
wdenk0f8c9762002-08-19 11:57:05 +000098
wdenk0f8c9762002-08-19 11:57:05 +000099/*
100 * Miscellaneous configurable options
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_LONGHELP /* undef to save memory */
103#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500104#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000106#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000108#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
110#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
111#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
114#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
wdenk0f8c9762002-08-19 11:57:05 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
121#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
122#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
wdenk0f8c9762002-08-19 11:57:05 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
125#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
wdenk0f8c9762002-08-19 11:57:05 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000128
wdenk0f8c9762002-08-19 11:57:05 +0000129/*
130 * Low Level Configuration Settings
131 * (address mappings, register initial values, etc.)
132 * You should know what you are doing if you make changes here.
133 */
134/*-----------------------------------------------------------------------
135 * Internal Memory Mapped Register
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
wdenk0f8c9762002-08-19 11:57:05 +0000138
139/*-----------------------------------------------------------------------
140 * Definitions for initial stack pointer and data area (in DPRAM)
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
wdenk0f8c9762002-08-19 11:57:05 +0000143#if defined (CONFIG_IVMS8_16M)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200144# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000145#elif defined (CONFIG_IVMS8_32M)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200146# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000147#elif defined (CONFIG_IVMS8_64M)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200148# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000149#endif
150
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200151#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000153
154/*-----------------------------------------------------------------------
155 * Start addresses for the final memory configuration
156 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_SDRAM_BASE 0x00000000
160#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenk0f8c9762002-08-19 11:57:05 +0000161#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000163#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk0f8c9762002-08-19 11:57:05 +0000165#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
167#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk0f8c9762002-08-19 11:57:05 +0000168
169/*
170 * For booting Linux, the board info and command line data
171 * have to be in the first 8 MB of memory, since this is
172 * the maximum mapped by the Linux kernel during initialization.
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000175/*-----------------------------------------------------------------------
176 * FLASH organization
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
179#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
182#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000183
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200184#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200185#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
186#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000187/*-----------------------------------------------------------------------
188 * Cache Configuration
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500191#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk0f8c9762002-08-19 11:57:05 +0000193#endif
194
195/*-----------------------------------------------------------------------
196 * SYPCR - System Protection Control 11-9
197 * SYPCR can only be written once after reset!
198 *-----------------------------------------------------------------------
199 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
200 */
201#if defined(CONFIG_WATCHDOG)
202# if defined (CONFIG_IVMS8_16M)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200204 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000205# elif defined (CONFIG_IVMS8_32M)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk0f8c9762002-08-19 11:57:05 +0000207 SYPCR_SWE | SYPCR_SWP)
208# elif defined (CONFIG_IVMS8_64M)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk0f8c9762002-08-19 11:57:05 +0000210 SYPCR_SWE | SYPCR_SWP)
211# endif
212#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000214#endif
215
216/*-----------------------------------------------------------------------
217 * SIUMCR - SIU Module Configuration 11-6
218 *-----------------------------------------------------------------------
219 * PCMCIA config., multi-function pin tri-state
220 */
221/* EARB, DBGC and DBPC are initialised by the HCW */
222/* => 0x000000C0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
wdenk0f8c9762002-08-19 11:57:05 +0000224
225/*-----------------------------------------------------------------------
226 * TBSCR - Time Base Status and Control 11-26
227 *-----------------------------------------------------------------------
228 * Clear Reference Interrupt Status, Timebase freezing enabled
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk0f8c9762002-08-19 11:57:05 +0000231
232/*-----------------------------------------------------------------------
233 * PISCR - Periodic Interrupt Status and Control 11-31
234 *-----------------------------------------------------------------------
235 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk0f8c9762002-08-19 11:57:05 +0000238
239/*-----------------------------------------------------------------------
240 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
241 *-----------------------------------------------------------------------
242 * Reset PLL lock status sticky bit, timer expired status bit and timer
243 * interrupt status bit, set PLL multiplication factor !
244 */
245/* 0x00B0C0C0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_PLPRCR \
wdenk0f8c9762002-08-19 11:57:05 +0000247 ( (11 << PLPRCR_MF_SHIFT) | \
248 PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
249 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
250 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
251 )
252
253/*-----------------------------------------------------------------------
254 * SCCR - System Clock and reset Control Register 15-27
255 *-----------------------------------------------------------------------
256 * Set clock output, timebase and RTC source and divider,
257 * power management and some other internal clocks
258 */
259#define SCCR_MASK SCCR_EBDF11
260/* 0x01800014 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
wdenk0f8c9762002-08-19 11:57:05 +0000262 SCCR_RTDIV | SCCR_RTSEL | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200263 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
wdenk0f8c9762002-08-19 11:57:05 +0000264 SCCR_EBDF00 | SCCR_DFSYNC00 | \
265 SCCR_DFBRG00 | SCCR_DFNL000 | \
266 SCCR_DFNH000 | SCCR_DFLCD101 | \
267 SCCR_DFALCD00)
268
269/*-----------------------------------------------------------------------
270 * RTCSC - Real-Time Clock Status and Control Register 11-27
271 *-----------------------------------------------------------------------
272 */
273/* 0x00C3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk0f8c9762002-08-19 11:57:05 +0000275
276
277/*-----------------------------------------------------------------------
278 * RCCR - RISC Controller Configuration Register 19-4
279 *-----------------------------------------------------------------------
280 */
281/* TIMEP=2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_RCCR 0x0200
wdenk0f8c9762002-08-19 11:57:05 +0000283
284/*-----------------------------------------------------------------------
285 * RMDS - RISC Microcode Development Support Control Register
286 *-----------------------------------------------------------------------
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_RMDS 0
wdenk0f8c9762002-08-19 11:57:05 +0000289
290/*-----------------------------------------------------------------------
291 *
292 * Interrupt Levels
293 *-----------------------------------------------------------------------
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
wdenk0f8c9762002-08-19 11:57:05 +0000296
297/*-----------------------------------------------------------------------
298 * PCMCIA stuff
299 *-----------------------------------------------------------------------
300 *
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
303#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
304#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
305#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
306#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
307#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
308#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
309#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk0f8c9762002-08-19 11:57:05 +0000310
311/*-----------------------------------------------------------------------
312 * IDE/ATA stuff
313 *-----------------------------------------------------------------------
314 */
315#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
316#define CONFIG_IDE_RESET 1 /* reset for ide supported */
317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */
319#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
wdenk0f8c9762002-08-19 11:57:05 +0000320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
322#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
323#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
wdenk0f8c9762002-08-19 11:57:05 +0000324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
326#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
327#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
wdenk0f8c9762002-08-19 11:57:05 +0000328
329/*-----------------------------------------------------------------------
330 *
331 *-----------------------------------------------------------------------
332 *
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_DER 0
wdenk0f8c9762002-08-19 11:57:05 +0000335
336/*
337 * Init Memory Controller:
338 *
339 * BR0 and OR0 (FLASH)
340 */
341
342#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
343
344/* used to re-map FLASH both when starting from SRAM or FLASH:
345 * restrict access enough to keep SRAM working (if any)
346 * but not too much to meddle with FLASH accesses
347 */
348/* EPROMs are 512kb */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
350#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
wdenk0f8c9762002-08-19 11:57:05 +0000351
352/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
wdenk0f8c9762002-08-19 11:57:05 +0000354 OR_SCY_5_CLK | OR_EHTR)
355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
357#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenk0f8c9762002-08-19 11:57:05 +0000358/* 16 bit, bank valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000360
361/*
362 * BR1/OR1 - ELIC SACCO bank @ 0xFE000000
363 *
364 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
365 */
366#define ELIC_SACCO_BASE 0xFE000000
367#define ELIC_SACCO_OR_AM 0xFFFF8000
368#define ELIC_SACCO_TIMING 0x00000F26
369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
371#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000372
373/*
374 * BR2/OR2 - ELIC EPIC bank @ 0xFE008000
375 *
376 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
377 */
378#define ELIC_EPIC_BASE 0xFE008000
379#define ELIC_EPIC_OR_AM 0xFFFF8000
380#define ELIC_EPIC_TIMING 0x00000F26
381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
383#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000384
385/*
386 * BR3/OR3: SDRAM
387 *
388 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
389 */
390#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
391#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
392#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
393
394#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
395
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
397#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000398
399/*
400 * BR4/OR4: not used
401 */
402
403/*
404 * BR5/OR5: SHARC ADSP-2165L
405 *
406 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
407 */
408#define SHARC_BASE 0xFE400000
409#define SHARC_OR_AM 0xFFC00000
410#define SHARC_TIMING 0x00000700
411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_OR5 (SHARC_OR_AM | SHARC_TIMING )
413#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
wdenk0f8c9762002-08-19 11:57:05 +0000414
415/*
416 * Memory Periodic Timer Prescaler
417 */
418
419/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_MBMR_PTB 204
wdenk0f8c9762002-08-19 11:57:05 +0000421
422/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
424#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000425
426/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
wdenk0f8c9762002-08-19 11:57:05 +0000428#if defined (CONFIG_IVMS8_16M)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000430#elif defined (CONFIG_IVMS8_32M)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000432#elif defined (CONFIG_IVMS8_64M)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
wdenk0f8c9762002-08-19 11:57:05 +0000434#endif
435
436
437/*
438 * MBMR settings for SDRAM
439 */
440
441#if defined (CONFIG_IVMS8_16M)
442 /* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200444 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
445 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
wdenk0f8c9762002-08-19 11:57:05 +0000446#elif defined (CONFIG_IVMS8_32M)
447/* 128 MBit SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
wdenk2535d602003-07-17 23:16:40 +0000449 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
450 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
wdenk0f8c9762002-08-19 11:57:05 +0000451#elif defined (CONFIG_IVMS8_64M)
452/* 128 MBit SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
wdenk2535d602003-07-17 23:16:40 +0000454 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
455 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
wdenk0f8c9762002-08-19 11:57:05 +0000456
457#endif
wdenk0f8c9762002-08-19 11:57:05 +0000458#endif /* __CONFIG_H */