blob: 038f4f4270ec1f1f94a011c11ae43251d37f2160 [file] [log] [blame]
Peter Tyser5da6f802009-06-30 17:26:01 -05001/*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
Peter Tyserc00ac252010-10-22 00:20:26 -050025 * xpedite517x board configuration file
Peter Tyser5da6f802009-06-30 17:26:01 -050026 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_MPC86xx 1 /* MPC86xx */
34#define CONFIG_MPC8641 1 /* MPC8641 specific */
35#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
36#define CONFIG_SYS_BOARD_NAME "XPedite5170"
John Schmoller92af65492010-10-22 00:20:24 -050037#define CONFIG_SYS_FORM_3U_VPX 1
Peter Tyser5da6f802009-06-30 17:26:01 -050038#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
39#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050040#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Peter Tyser5da6f802009-06-30 17:26:01 -050041#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
42#define CONFIG_ALTIVEC 1
43
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044#define CONFIG_SYS_TEXT_BASE 0xfff00000
45
Peter Tyser5da6f802009-06-30 17:26:01 -050046#define CONFIG_PCI 1 /* Enable PCI/PCIE */
47#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
48#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
49#define CONFIG_PCIE1 1 /* PCIE controler 1 */
50#define CONFIG_PCIE2 1 /* PCIE controler 2 */
51#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
52#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
54
55/*
56 * DDR config
57 */
58#define CONFIG_FSL_DDR2
59#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
60#define CONFIG_DDR_SPD
61#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
62#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
63#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
64#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
65#define CONFIG_NUM_DDR_CONTROLLERS 2
66#define CONFIG_DIMM_SLOTS_PER_CTLR 1
67#define CONFIG_CHIP_SELECTS_PER_CTRL 1
68#define CONFIG_DDR_ECC
69#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
70#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
71#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
72#define CONFIG_VERY_BIG_RAM
73#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
74
75/*
76 * virtual address to be used for temporary mappings. There
77 * should be 128k free at this VA.
78 */
79#define CONFIG_SYS_SCRATCH_VA 0xe0000000
80
81#ifndef __ASSEMBLY__
82extern unsigned long get_board_sys_clk(unsigned long dummy);
83#endif
84
85#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
86
87/*
88 * L2CR setup
89 */
90#define CONFIG_SYS_L2
91#define L2_INIT 0
92#define L2_ENABLE (L2CR_L2E)
93
94/*
95 * Base addresses -- Note these are effective addresses where the
96 * actual resources get mapped (not physical addresses)
97 */
98#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
99#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
100#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
101#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
102#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
103#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
Peter Tyser5da6f802009-06-30 17:26:01 -0500104
105/*
106 * Diagnostics
107 */
108#define CONFIG_SYS_ALT_MEMTEST
109#define CONFIG_SYS_MEMTEST_START 0x10000000
110#define CONFIG_SYS_MEMTEST_END 0x20000000
Peter Tyser66a8b442010-10-22 00:20:33 -0500111#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
112 CONFIG_SYS_POST_I2C)
113#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
114 CONFIG_SYS_I2C_DS4510_ADDR, \
115 CONFIG_SYS_I2C_EEPROM_ADDR, \
116 CONFIG_SYS_I2C_LM90_ADDR, \
117 CONFIG_SYS_I2C_PCA9553_ADDR, \
118 CONFIG_SYS_I2C_PCA953X_ADDR0, \
119 CONFIG_SYS_I2C_PCA953X_ADDR1, \
120 CONFIG_SYS_I2C_PCA953X_ADDR2, \
121 CONFIG_SYS_I2C_PCA953X_ADDR3, \
122 CONFIG_SYS_I2C_PEX8518_ADDR, \
123 CONFIG_SYS_I2C_RTC_ADDR}
124/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
125#define I2C_ADDR_IGNORE_LIST {0x50}
Peter Tyser5da6f802009-06-30 17:26:01 -0500126
127/*
128 * Memory map
129 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
130 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
131 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
132 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
133 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
134 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
135 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
136 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
137 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
138 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
139 */
140
Kumar Gala202d9482009-09-15 22:21:58 -0500141#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
Peter Tyser5da6f802009-06-30 17:26:01 -0500142
143/*
144 * NAND flash configuration
145 */
146#define CONFIG_SYS_NAND_BASE 0xef800000
147#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
148#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
149#define CONFIG_SYS_MAX_NAND_DEVICE 2
150#define CONFIG_NAND_ACTL
151#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
152#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
153#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
154#define CONFIG_SYS_NAND_ACTL_DELAY 25
155#define CONFIG_SYS_NAND_QUIET_TEST
156#define CONFIG_JFFS2_NAND
157
158/*
159 * NOR flash configuration
160 */
161#define CONFIG_SYS_FLASH_BASE 0xf8000000
162#define CONFIG_SYS_FLASH_BASE2 0xf0000000
163#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
164#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
165#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
166#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
167#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
168#define CONFIG_FLASH_CFI_DRIVER
169#define CONFIG_SYS_FLASH_CFI
170#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
171#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
172 {0xf7f00000, 0xc0000} }
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200173#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Peter Tyser5da6f802009-06-30 17:26:01 -0500174#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
175
176/*
177 * Chip select configuration
178 */
179/* NOR Flash 0 on CS0 */
180#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
181 BR_PS_16 |\
182 BR_V)
183#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
184 OR_GPCM_CSNT |\
185 OR_GPCM_XACS |\
186 OR_GPCM_ACS_DIV2 |\
187 OR_GPCM_SCY_8 |\
188 OR_GPCM_TRLX |\
189 OR_GPCM_EHTR |\
190 OR_GPCM_EAD)
191
192/* NOR Flash 1 on CS1 */
193#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
194 BR_PS_16 |\
195 BR_V)
196#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
197
198/* NAND flash on CS2 */
199#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
200 BR_PS_8 |\
201 BR_V)
202#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
203 OR_GPCM_BCTLD |\
204 OR_GPCM_CSNT |\
205 OR_GPCM_ACS_DIV4 |\
206 OR_GPCM_SCY_4 |\
207 OR_GPCM_TRLX |\
208 OR_GPCM_EHTR)
209
210/* Optional NAND flash on CS3 */
211#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
212 BR_PS_8 |\
213 BR_V)
214#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
215
216/*
217 * Use L1 as initial stack
218 */
219#define CONFIG_SYS_INIT_RAM_LOCK 1
220#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200221#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
Peter Tyser5da6f802009-06-30 17:26:01 -0500222
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200223#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Peter Tyser5da6f802009-06-30 17:26:01 -0500224#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
225
226#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
227#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
228
229/*
230 * Serial Port
231 */
232#define CONFIG_CONS_INDEX 1
233#define CONFIG_SYS_NS16550
234#define CONFIG_SYS_NS16550_SERIAL
235#define CONFIG_SYS_NS16550_REG_SIZE 1
236#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
237#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
238#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
239#define CONFIG_SYS_BAUDRATE_TABLE \
240 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
241#define CONFIG_BAUDRATE 115200
242#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
243#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
244
245/*
246 * Use the HUSH parser
247 */
248#define CONFIG_SYS_HUSH_PARSER
Peter Tyser5da6f802009-06-30 17:26:01 -0500249
250/*
251 * Pass open firmware flat tree
252 */
253#define CONFIG_OF_LIBFDT 1
254#define CONFIG_OF_BOARD_SETUP 1
255#define CONFIG_OF_STDOUT_VIA_ALIAS 1
256
Peter Tyser5da6f802009-06-30 17:26:01 -0500257/*
258 * I2C
259 */
260#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
261#define CONFIG_HARD_I2C /* I2C with hardware support */
262#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */
263#define CONFIG_SYS_I2C_SLAVE 0x7F
264#define CONFIG_SYS_I2C_OFFSET 0x3000
265#define CONFIG_SYS_I2C2_OFFSET 0x3100
266#define CONFIG_I2C_MULTI_BUS
Peter Tyser5da6f802009-06-30 17:26:01 -0500267
268/* PEX8518 slave I2C interface */
269#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
270
271/* I2C DS1631 temperature sensor */
272#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
273#define CONFIG_DTT_DS1621
274#define CONFIG_DTT_SENSORS { 0 }
Peter Tyser66a8b442010-10-22 00:20:33 -0500275#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
Peter Tyser5da6f802009-06-30 17:26:01 -0500276
277/* I2C EEPROM - AT24C128B */
278#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
279#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
280#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
281#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
282
283/* I2C RTC */
284#define CONFIG_RTC_M41T11 1
285#define CONFIG_SYS_I2C_RTC_ADDR 0x68
286#define CONFIG_SYS_M41T11_BASE_YEAR 2000
287
288/* GPIO/EEPROM/SRAM */
289#define CONFIG_DS4510
290#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
291
292/* GPIO */
293#define CONFIG_PCA953X
294#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
295#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
296#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
297#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
298#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
Peter Tyser66a8b442010-10-22 00:20:33 -0500299#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
Peter Tyser5da6f802009-06-30 17:26:01 -0500300
301/*
302 * PU = pulled high, PD = pulled low
303 * I = input, O = output, IO = input/output
304 */
305/* PCA9557 @ 0x18*/
306#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
307#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
308#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
309#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
310#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
311#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
312
313/* PCA9557 @ 0x1c*/
314#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
315#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
316#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
317#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
318#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
319#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
320#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
321#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
322
323/* PCA9557 @ 0x1e*/
324#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
325#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
326#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
327#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
328#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
329#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
330#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
331
332/* PCA9557 @ 0x1f */
333#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
334#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
335#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
336#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
337
338/*
339 * General PCI
340 * Memory space is mapped 1-1, but I/O space must start from 0.
341 */
342/* PCIE1 - PEX8518 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500343#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
344#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Peter Tyser5da6f802009-06-30 17:26:01 -0500345#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500346#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Peter Tyser5da6f802009-06-30 17:26:01 -0500347#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
348#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
349
350/* PCIE2 - VPX P1 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500351#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
352#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Peter Tyser5da6f802009-06-30 17:26:01 -0500353#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500354#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Peter Tyser5da6f802009-06-30 17:26:01 -0500355#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
356#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
357
358/*
359 * Networking options
360 */
361#define CONFIG_TSEC_ENET /* tsec ethernet support */
362#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Peter Tyser5da6f802009-06-30 17:26:01 -0500363#define CONFIG_MII 1 /* MII PHY management */
364#define CONFIG_ETHPRIME "eTSEC1"
365
366#define CONFIG_TSEC1 1
367#define CONFIG_TSEC1_NAME "eTSEC1"
368#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
369#define TSEC1_PHY_ADDR 1
370#define TSEC1_PHYIDX 0
371#define CONFIG_HAS_ETH0
372
373#define CONFIG_TSEC2 1
374#define CONFIG_TSEC2_NAME "eTSEC2"
375#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
376#define TSEC2_PHY_ADDR 2
377#define TSEC2_PHYIDX 0
378#define CONFIG_HAS_ETH1
379
380/*
381 * BAT mappings
382 */
383#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
384#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
385 BATL_PP_RW |\
386 BATL_CACHEINHIBIT |\
387 BATL_GUARDEDSTORAGE)
388#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
389 BATU_BL_1M |\
390 BATU_VS |\
391 BATU_VP)
392#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
393 BATL_PP_RW |\
394 BATL_CACHEINHIBIT)
395#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
396#endif
397
398/*
399 * BAT0 2G Cacheable, non-guarded
400 * 0x0000_0000 2G DDR
401 */
402#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
403#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
404#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
405#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
406
407/*
408 * BAT1 1G Cache-inhibited, guarded
409 * 0x8000_0000 1G PCI-Express 1 Memory
410 */
411#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
412 BATL_PP_RW |\
413 BATL_CACHEINHIBIT |\
414 BATL_GUARDEDSTORAGE)
415#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
416 BATU_BL_1G |\
417 BATU_VS |\
418 BATU_VP)
419#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
420 BATL_PP_RW |\
421 BATL_CACHEINHIBIT)
422#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
423
424/*
425 * BAT2 512M Cache-inhibited, guarded
426 * 0xc000_0000 512M PCI-Express 2 Memory
427 */
428#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
429 BATL_PP_RW |\
430 BATL_CACHEINHIBIT |\
431 BATL_GUARDEDSTORAGE)
432#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
433 BATU_BL_512M |\
434 BATU_VS |\
435 BATU_VP)
436#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
437 BATL_PP_RW |\
438 BATL_CACHEINHIBIT)
439#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
440
441/*
442 * BAT3 1M Cache-inhibited, guarded
443 * 0xe000_0000 1M CCSR
444 */
445#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
446 BATL_PP_RW |\
447 BATL_CACHEINHIBIT |\
448 BATL_GUARDEDSTORAGE)
449#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
450 BATU_BL_1M |\
451 BATU_VS |\
452 BATU_VP)
453#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
454 BATL_PP_RW |\
455 BATL_CACHEINHIBIT)
456#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
457
458/*
459 * BAT4 32M Cache-inhibited, guarded
460 * 0xe200_0000 16M PCI-Express 1 I/O
461 * 0xe300_0000 16M PCI-Express 2 I/0
462 */
463#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
464 BATL_PP_RW |\
465 BATL_CACHEINHIBIT |\
466 BATL_GUARDEDSTORAGE)
467#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
468 BATU_BL_32M |\
469 BATU_VS |\
470 BATU_VP)
471#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
472 BATL_PP_RW |\
473 BATL_CACHEINHIBIT)
474#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
475
476/*
477 * BAT5 128K Cacheable, non-guarded
478 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
479 */
480#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
481 BATL_PP_RW |\
482 BATL_MEMCOHERENCE)
483#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
484 BATU_BL_128K |\
485 BATU_VS |\
486 BATU_VP)
487#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
488#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
489
490/*
491 * BAT6 256M Cache-inhibited, guarded
492 * 0xf000_0000 256M FLASH
493 */
494#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
495 BATL_PP_RW |\
496 BATL_CACHEINHIBIT |\
497 BATL_GUARDEDSTORAGE)
498#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
499 BATU_BL_256M |\
500 BATU_VS |\
501 BATU_VP)
502#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
503 BATL_PP_RW |\
504 BATL_MEMCOHERENCE)
505#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
506
507/* Map the last 1M of flash where we're running from reset */
508#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
509 BATL_PP_RW |\
510 BATL_CACHEINHIBIT |\
511 BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200512#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
Peter Tyser5da6f802009-06-30 17:26:01 -0500513 BATU_BL_1M |\
514 BATU_VS |\
515 BATU_VP)
516#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
517 BATL_PP_RW |\
518 BATL_MEMCOHERENCE)
519#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
520
521/*
522 * BAT7 64M Cache-inhibited, guarded
523 * 0xe800_0000 64K NAND FLASH
524 * 0xe804_0000 128K DUART Registers
525 */
526#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
527 BATL_PP_RW |\
528 BATL_CACHEINHIBIT |\
529 BATL_GUARDEDSTORAGE)
530#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
531 BATU_BL_512K |\
532 BATU_VS |\
533 BATU_VP)
534#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
535 BATL_PP_RW |\
536 BATL_CACHEINHIBIT)
537#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
538
539/*
540 * Command configuration.
541 */
542#include <config_cmd_default.h>
543
544#define CONFIG_CMD_ASKENV
545#define CONFIG_CMD_DATE
546#define CONFIG_CMD_DHCP
547#define CONFIG_CMD_DS4510
548#define CONFIG_CMD_DS4510_INFO
549#define CONFIG_CMD_DTT
550#define CONFIG_CMD_EEPROM
551#define CONFIG_CMD_ELF
552#define CONFIG_CMD_SAVEENV
553#define CONFIG_CMD_FLASH
554#define CONFIG_CMD_I2C
555#define CONFIG_CMD_IRQ
556#define CONFIG_CMD_JFFS2
557#define CONFIG_CMD_MII
558#define CONFIG_CMD_NAND
559#define CONFIG_CMD_NET
560#define CONFIG_CMD_PCA953X
561#define CONFIG_CMD_PCA953X_INFO
562#define CONFIG_CMD_PCI
John Schmoller96d61602010-10-22 00:20:23 -0500563#define CONFIG_CMD_PCI_ENUM
Peter Tyser5da6f802009-06-30 17:26:01 -0500564#define CONFIG_CMD_PING
565#define CONFIG_CMD_REGINFO
566#define CONFIG_CMD_SNTP
567
568/*
569 * Miscellaneous configurable options
570 */
571#define CONFIG_SYS_LONGHELP /* undef to save memory */
572#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
573#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
574#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
575#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
576#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
577#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
578#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
579#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
580#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
581#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
582#define CONFIG_PANIC_HANG /* do not reset board on panic */
583#define CONFIG_PREBOOT /* enable preboot variable */
584#define CONFIG_FIT 1
585#define CONFIG_FIT_VERBOSE 1
586#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
587
588/*
589 * For booting Linux, the board info and command line data
590 * have to be in the first 16 MB of memory, since this is
591 * the maximum mapped by the Linux kernel during initialization.
592 */
593#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500594#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyser5da6f802009-06-30 17:26:01 -0500595
596/*
Peter Tyser5da6f802009-06-30 17:26:01 -0500597 * Environment Configuration
598 */
599#define CONFIG_ENV_IS_IN_FLASH 1
600#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
601#define CONFIG_ENV_SIZE 0x8000
602#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
603
604/*
605 * Flash memory map:
606 * fffc0000 - ffffffff Pri FDT (256KB)
607 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
608 * fff00000 - fff7ffff Pri U-Boot (512 KB)
609 * fef00000 - ffefffff Pri OS image (16MB)
610 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
611 *
612 * f7fc0000 - f7ffffff Sec FDT (256KB)
613 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
614 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
615 * f6f00000 - f7efffff Sec OS image (16MB)
616 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
617 */
618#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000)
619#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000)
620#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000)
621#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000)
622#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
623#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
624
625#define CONFIG_PROG_UBOOT1 \
626 "$download_cmd $loadaddr $ubootfile; " \
627 "if test $? -eq 0; then " \
628 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
629 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
630 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
631 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
632 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
633 "if test $? -ne 0; then " \
634 "echo PROGRAM FAILED; " \
635 "else; " \
636 "echo PROGRAM SUCCEEDED; " \
637 "fi; " \
638 "else; " \
639 "echo DOWNLOAD FAILED; " \
640 "fi;"
641
642#define CONFIG_PROG_UBOOT2 \
643 "$download_cmd $loadaddr $ubootfile; " \
644 "if test $? -eq 0; then " \
645 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
646 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
647 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
648 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
649 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
650 "if test $? -ne 0; then " \
651 "echo PROGRAM FAILED; " \
652 "else; " \
653 "echo PROGRAM SUCCEEDED; " \
654 "fi; " \
655 "else; " \
656 "echo DOWNLOAD FAILED; " \
657 "fi;"
658
659#define CONFIG_BOOT_OS_NET \
660 "$download_cmd $osaddr $osfile; " \
661 "if test $? -eq 0; then " \
662 "if test -n $fdtaddr; then " \
663 "$download_cmd $fdtaddr $fdtfile; " \
664 "if test $? -eq 0; then " \
665 "bootm $osaddr - $fdtaddr; " \
666 "else; " \
667 "echo FDT DOWNLOAD FAILED; " \
668 "fi; " \
669 "else; " \
670 "bootm $osaddr; " \
671 "fi; " \
672 "else; " \
673 "echo OS DOWNLOAD FAILED; " \
674 "fi;"
675
676#define CONFIG_PROG_OS1 \
677 "$download_cmd $osaddr $osfile; " \
678 "if test $? -eq 0; then " \
679 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
680 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
681 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
682 "if test $? -ne 0; then " \
683 "echo OS PROGRAM FAILED; " \
684 "else; " \
685 "echo OS PROGRAM SUCCEEDED; " \
686 "fi; " \
687 "else; " \
688 "echo OS DOWNLOAD FAILED; " \
689 "fi;"
690
691#define CONFIG_PROG_OS2 \
692 "$download_cmd $osaddr $osfile; " \
693 "if test $? -eq 0; then " \
694 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
695 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
696 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
697 "if test $? -ne 0; then " \
698 "echo OS PROGRAM FAILED; " \
699 "else; " \
700 "echo OS PROGRAM SUCCEEDED; " \
701 "fi; " \
702 "else; " \
703 "echo OS DOWNLOAD FAILED; " \
704 "fi;"
705
706#define CONFIG_PROG_FDT1 \
707 "$download_cmd $fdtaddr $fdtfile; " \
708 "if test $? -eq 0; then " \
709 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
710 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
711 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
712 "if test $? -ne 0; then " \
713 "echo FDT PROGRAM FAILED; " \
714 "else; " \
715 "echo FDT PROGRAM SUCCEEDED; " \
716 "fi; " \
717 "else; " \
718 "echo FDT DOWNLOAD FAILED; " \
719 "fi;"
720
721#define CONFIG_PROG_FDT2 \
722 "$download_cmd $fdtaddr $fdtfile; " \
723 "if test $? -eq 0; then " \
724 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
725 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
726 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
727 "if test $? -ne 0; then " \
728 "echo FDT PROGRAM FAILED; " \
729 "else; " \
730 "echo FDT PROGRAM SUCCEEDED; " \
731 "fi; " \
732 "else; " \
733 "echo FDT DOWNLOAD FAILED; " \
734 "fi;"
735
736#define CONFIG_EXTRA_ENV_SETTINGS \
737 "autoload=yes\0" \
738 "download_cmd=tftp\0" \
739 "console_args=console=ttyS0,115200\0" \
740 "root_args=root=/dev/nfs rw\0" \
741 "misc_args=ip=on\0" \
742 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
743 "bootfile=/home/user/file\0" \
Peter Tyserc00ac252010-10-22 00:20:26 -0500744 "osfile=/home/user/board.uImage\0" \
745 "fdtfile=/home/user/board.dtb\0" \
Peter Tyser5da6f802009-06-30 17:26:01 -0500746 "ubootfile=/home/user/u-boot.bin\0" \
747 "fdtaddr=c00000\0" \
748 "osaddr=0x1000000\0" \
749 "loadaddr=0x1000000\0" \
750 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
751 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
752 "prog_os1="CONFIG_PROG_OS1"\0" \
753 "prog_os2="CONFIG_PROG_OS2"\0" \
754 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
755 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
756 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
757 "bootcmd_flash1=run set_bootargs; " \
758 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
759 "bootcmd_flash2=run set_bootargs; " \
760 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
761 "bootcmd=run bootcmd_flash1\0"
762#endif /* __CONFIG_H */